{"id":"https://openalex.org/W4398169008","doi":"https://doi.org/10.1145/3649455","title":"FASA-DRAM: Reducing DRAM Latency with Destructive Activation and Delayed Restoration","display_name":"FASA-DRAM: Reducing DRAM Latency with Destructive Activation and Delayed Restoration","publication_year":2024,"publication_date":"2024-05-21","ids":{"openalex":"https://openalex.org/W4398169008","doi":"https://doi.org/10.1145/3649455"},"language":"en","primary_location":{"id":"doi:10.1145/3649455","is_oa":true,"landing_page_url":"https://doi.org/10.1145/3649455","pdf_url":"https://dl.acm.org/doi/pdf/10.1145/3649455","source":{"id":"https://openalex.org/S26056741","display_name":"ACM Transactions on Architecture and Code Optimization","issn_l":"1544-3566","issn":["1544-3566","1544-3973"],"is_oa":true,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319798","host_organization_name":"Association for Computing Machinery","host_organization_lineage":["https://openalex.org/P4310319798"],"host_organization_lineage_names":["Association for Computing Machinery"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"ACM Transactions on Architecture and Code Optimization","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"diamond","oa_url":"https://dl.acm.org/doi/pdf/10.1145/3649455","any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5101488186","display_name":"Haitao Du","orcid":"https://orcid.org/0000-0002-4203-6381"},"institutions":[{"id":"https://openalex.org/I126520041","display_name":"University of Science and Technology of China","ror":"https://ror.org/04c4dkn09","country_code":"CN","type":"education","lineage":["https://openalex.org/I126520041","https://openalex.org/I19820366"]}],"countries":["CN"],"is_corresponding":true,"raw_author_name":"Haitao Du","raw_affiliation_strings":["University of Science and Technology of China, Hefei, China"],"affiliations":[{"raw_affiliation_string":"University of Science and Technology of China, Hefei, China","institution_ids":["https://openalex.org/I126520041"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5012605049","display_name":"Yuhan Qin","orcid":"https://orcid.org/0009-0003-9179-938X"},"institutions":[{"id":"https://openalex.org/I126520041","display_name":"University of Science and Technology of China","ror":"https://ror.org/04c4dkn09","country_code":"CN","type":"education","lineage":["https://openalex.org/I126520041","https://openalex.org/I19820366"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Yuhan Qin","raw_affiliation_strings":["University of Science and Technology of China, Hefei, China"],"affiliations":[{"raw_affiliation_string":"University of Science and Technology of China, Hefei, China","institution_ids":["https://openalex.org/I126520041"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100423614","display_name":"Song Chen","orcid":"https://orcid.org/0000-0003-0341-3428"},"institutions":[{"id":"https://openalex.org/I126520041","display_name":"University of Science and Technology of China","ror":"https://ror.org/04c4dkn09","country_code":"CN","type":"education","lineage":["https://openalex.org/I126520041","https://openalex.org/I19820366"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Song Chen","raw_affiliation_strings":["University of Science and Technology of China, Hefei, China"],"affiliations":[{"raw_affiliation_string":"University of Science and Technology of China, Hefei, China","institution_ids":["https://openalex.org/I126520041"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5033886915","display_name":"Yi Kang","orcid":"https://orcid.org/0009-0004-3092-5626"},"institutions":[{"id":"https://openalex.org/I126520041","display_name":"University of Science and Technology of China","ror":"https://ror.org/04c4dkn09","country_code":"CN","type":"education","lineage":["https://openalex.org/I126520041","https://openalex.org/I19820366"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Yi Kang","raw_affiliation_strings":["University of Science and Technology of China, Hefei, China"],"affiliations":[{"raw_affiliation_string":"University of Science and Technology of China, Hefei, China","institution_ids":["https://openalex.org/I126520041"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5101488186"],"corresponding_institution_ids":["https://openalex.org/I126520041"],"apc_list":null,"apc_paid":null,"fwci":2.9365,"has_fulltext":false,"cited_by_count":6,"citation_normalized_percentile":{"value":0.91858429,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":94,"max":98},"biblio":{"volume":"21","issue":"2","first_page":"1","last_page":"27"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/dram","display_name":"Dram","score":0.9659799337387085},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7135214805603027},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.6230476498603821},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5062188506126404},{"id":"https://openalex.org/keywords/reliability-engineering","display_name":"Reliability engineering","score":0.4487522840499878},{"id":"https://openalex.org/keywords/cas-latency","display_name":"CAS latency","score":0.4340746998786926},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.2924356460571289},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.2550166845321655},{"id":"https://openalex.org/keywords/memory-controller","display_name":"Memory controller","score":0.10687211155891418},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.08937600255012512},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.08912801742553711},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.06677180528640747}],"concepts":[{"id":"https://openalex.org/C7366592","wikidata":"https://www.wikidata.org/wiki/Q1255620","display_name":"Dram","level":2,"score":0.9659799337387085},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7135214805603027},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.6230476498603821},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5062188506126404},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.4487522840499878},{"id":"https://openalex.org/C189930140","wikidata":"https://www.wikidata.org/wiki/Q1112878","display_name":"CAS latency","level":4,"score":0.4340746998786926},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.2924356460571289},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.2550166845321655},{"id":"https://openalex.org/C100800780","wikidata":"https://www.wikidata.org/wiki/Q1175867","display_name":"Memory controller","level":3,"score":0.10687211155891418},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.08937600255012512},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.08912801742553711},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.06677180528640747}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/3649455","is_oa":true,"landing_page_url":"https://doi.org/10.1145/3649455","pdf_url":"https://dl.acm.org/doi/pdf/10.1145/3649455","source":{"id":"https://openalex.org/S26056741","display_name":"ACM Transactions on Architecture and Code Optimization","issn_l":"1544-3566","issn":["1544-3566","1544-3973"],"is_oa":true,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319798","host_organization_name":"Association for Computing Machinery","host_organization_lineage":["https://openalex.org/P4310319798"],"host_organization_lineage_names":["Association for Computing Machinery"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"ACM Transactions on Architecture and Code Optimization","raw_type":"journal-article"}],"best_oa_location":{"id":"doi:10.1145/3649455","is_oa":true,"landing_page_url":"https://doi.org/10.1145/3649455","pdf_url":"https://dl.acm.org/doi/pdf/10.1145/3649455","source":{"id":"https://openalex.org/S26056741","display_name":"ACM Transactions on Architecture and Code Optimization","issn_l":"1544-3566","issn":["1544-3566","1544-3973"],"is_oa":true,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319798","host_organization_name":"Association for Computing Machinery","host_organization_lineage":["https://openalex.org/P4310319798"],"host_organization_lineage_names":["Association for Computing Machinery"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"ACM Transactions on Architecture and Code Optimization","raw_type":"journal-article"},"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy","score":0.9200000166893005}],"awards":[{"id":"https://openalex.org/G4027129818","display_name":null,"funder_award_id":"2019YFB2204800","funder_id":"https://openalex.org/F4320335777","funder_display_name":"National Key Research and Development Program of China"}],"funders":[{"id":"https://openalex.org/F4320335777","display_name":"National Key Research and Development Program of China","ror":null}],"has_content":{"pdf":true,"grobid_xml":false},"content_urls":{"pdf":"https://content.openalex.org/works/W4398169008.pdf"},"referenced_works_count":38,"referenced_works":["https://openalex.org/W1515422725","https://openalex.org/W1578894366","https://openalex.org/W2036895660","https://openalex.org/W2053768423","https://openalex.org/W2069345435","https://openalex.org/W2102480477","https://openalex.org/W2118811116","https://openalex.org/W2119092821","https://openalex.org/W2121256363","https://openalex.org/W2129381159","https://openalex.org/W2129991978","https://openalex.org/W2132269953","https://openalex.org/W2156226964","https://openalex.org/W2157116240","https://openalex.org/W2159908132","https://openalex.org/W2164586147","https://openalex.org/W2169370030","https://openalex.org/W2169875292","https://openalex.org/W2238633138","https://openalex.org/W2321746411","https://openalex.org/W2412593758","https://openalex.org/W2414926609","https://openalex.org/W2607352011","https://openalex.org/W2761132374","https://openalex.org/W2808751340","https://openalex.org/W2914280573","https://openalex.org/W2953044030","https://openalex.org/W3004300886","https://openalex.org/W3006586535","https://openalex.org/W3016460116","https://openalex.org/W3033124768","https://openalex.org/W3134718172","https://openalex.org/W3192890818","https://openalex.org/W3205305497","https://openalex.org/W4206782120","https://openalex.org/W4238816702","https://openalex.org/W4242052363","https://openalex.org/W4254778370"],"related_works":["https://openalex.org/W4293430534","https://openalex.org/W2342813629","https://openalex.org/W3150934690","https://openalex.org/W4297812927","https://openalex.org/W2335743642","https://openalex.org/W2800412005","https://openalex.org/W1976244802","https://openalex.org/W1992487929","https://openalex.org/W2083934844","https://openalex.org/W4386903460"],"abstract_inverted_index":{"DRAM":[0,156,212,219],"memory":[1,55,63],"is":[2,128,144,158],"a":[3],"performance":[4,105,206,237],"bottleneck":[5],"for":[6,220],"many":[7],"applications,":[8],"due":[9],"to":[10,28,53,189],"its":[11],"high":[12],"access":[13,56],"latency.":[14,37],"Previous":[15],"work":[16],"has":[17],"mainly":[18],"focused":[19],"on":[20],"data":[21,67,84,100,118,136,153],"locality,":[22,68],"introducing":[23],"small":[24],"but":[25],"fast":[26,88],"regions":[27],"cache":[29,90],"frequently":[30],"accessed":[31],"data,":[32],"thereby":[33],"reducing":[34],"the":[35,62,87,95,104,117,138,151,155,162,172,204],"average":[36,205,211],"However,":[38],"these":[39],"locality-based":[40],"designs":[41,234],"have":[42,73],"three":[43],"challenges":[44],"in":[45,235],"modern":[46],"multi-core":[47],"systems:":[48],"(1)":[49],"inter-application":[50],"interference":[51],"leads":[52],"random":[54],"traffic,":[57],"(2)":[58],"fairness":[59],"issues":[60],"prevent":[61],"controller":[64],"from":[65,167],"over-prioritizing":[66],"and":[69,77,91,106,169,185,194,209,238],"(3)":[70],"write-intensive":[71],"applications":[72],"much":[74],"lower":[75],"locality":[76],"evict":[78],"substantial":[79],"dirty":[80],"entries.":[81],"With":[82],"frequent":[83],"movement":[85,119],"between":[86],"in-DRAM":[89,110,139,192],"slow":[92],"regular":[93],"arrays,":[94],"overhead":[96],"induced":[97],"by":[98,207,215],"moving":[99],"may":[101],"even":[102],"offset":[103],"energy":[107,213,239],"benefits":[108],"of":[109],"caching.":[111],"In":[112],"this":[113],"article,":[114],"we":[115],"decouple":[116],"process":[120],"into":[121,137],"two":[122],"distinct":[123],"phases.":[124],"The":[125,141],"first":[126],"phase":[127,143,166],"Load-Reduced":[129],"Destructive":[130],"Activation":[131],"(LRDA),":[132],"which":[133,149],"destructively":[134],"promotes":[135],"cache.":[140],"second":[142],"Delayed":[145],"Cycle-Stealing":[146],"Restoration":[147],"(DCSR),":[148],"restores":[150],"original":[152],"when":[154],"bank":[157],"idle.":[159],"LRDA":[160],"decouples":[161],"most":[163],"time-consuming":[164],"restoration":[165,173,187],"activation,":[168],"DCSR":[170],"hides":[171],"latency":[174],"through":[175],"prevalent":[176],"bank-level":[177],"parallelism.":[178],"We":[179],"propose":[180],"FASA-DRAM,":[181],"incorporating":[182],"destructive":[183],"activation":[184],"delayed":[186],"techniques":[188],"enable":[190],"both":[191,236],"caching":[193],"proactive":[195],"latency-hiding":[196],"mechanisms.":[197],"Our":[198],"evaluation":[199],"shows":[200],"that":[201],"FASA-DRAM":[202,231],"improves":[203],"19.9%":[208],"reduces":[210],"consumption":[214],"18.1%":[216],"over":[217],"DDR4":[218],"four-core":[221],"workloads,":[222],"with":[223],"less":[224],"than":[225],"3.4%":[226],"extra":[227],"area":[228],"overhead.":[229],"Furthermore,":[230],"outperforms":[232],"state-of-the-art":[233],"efficiency.":[240]},"counts_by_year":[{"year":2025,"cited_by_count":4},{"year":2024,"cited_by_count":2}],"updated_date":"2026-03-27T05:58:40.876381","created_date":"2025-10-10T00:00:00"}
