{"id":"https://openalex.org/W4393970812","doi":"https://doi.org/10.1145/3648115.3648134","title":"Optimisation and Evaluation of Breadth First Search with oneAPI/SYCL on Intel FPGAs: from Describing Algorithms to Describing Architectures","display_name":"Optimisation and Evaluation of Breadth First Search with oneAPI/SYCL on Intel FPGAs: from Describing Algorithms to Describing Architectures","publication_year":2024,"publication_date":"2024-04-05","ids":{"openalex":"https://openalex.org/W4393970812","doi":"https://doi.org/10.1145/3648115.3648134"},"language":"en","primary_location":{"id":"doi:10.1145/3648115.3648134","is_oa":true,"landing_page_url":"https://doi.org/10.1145/3648115.3648134","pdf_url":null,"source":null,"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 12th International Workshop on OpenCL and SYCL","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"gold","oa_url":"https://doi.org/10.1145/3648115.3648134","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5048181168","display_name":"Kaan Olgu","orcid":"https://orcid.org/0000-0003-0351-2055"},"institutions":[{"id":"https://openalex.org/I36234482","display_name":"University of Bristol","ror":"https://ror.org/0524sp257","country_code":"GB","type":"education","lineage":["https://openalex.org/I36234482"]}],"countries":["GB"],"is_corresponding":true,"raw_author_name":"Kaan Olgu","raw_affiliation_strings":["School of Electrical & Electronics Engineering, University of Bristol, United Kingdom"],"affiliations":[{"raw_affiliation_string":"School of Electrical & Electronics Engineering, University of Bristol, United Kingdom","institution_ids":["https://openalex.org/I36234482"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5009852288","display_name":"Tobias Kenter","orcid":"https://orcid.org/0000-0002-5088-0267"},"institutions":[{"id":"https://openalex.org/I206945453","display_name":"Paderborn University","ror":"https://ror.org/058kzsd48","country_code":"DE","type":"education","lineage":["https://openalex.org/I206945453"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Tobias Kenter","raw_affiliation_strings":["Paderborn Center for Parallel Computing & Department of Computer Science, Paderborn University, Germany"],"affiliations":[{"raw_affiliation_string":"Paderborn Center for Parallel Computing & Department of Computer Science, Paderborn University, Germany","institution_ids":["https://openalex.org/I206945453"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5005255540","display_name":"Jose Nunez\u2010Yanez","orcid":"https://orcid.org/0000-0002-5153-5481"},"institutions":[{"id":"https://openalex.org/I102134673","display_name":"Link\u00f6ping University","ror":"https://ror.org/05ynxx418","country_code":"SE","type":"education","lineage":["https://openalex.org/I102134673"]}],"countries":["SE"],"is_corresponding":false,"raw_author_name":"Jose Nunez-Yanez","raw_affiliation_strings":["Dept. Electrical Engineering, Linkoping University, Sweden"],"affiliations":[{"raw_affiliation_string":"Dept. Electrical Engineering, Linkoping University, Sweden","institution_ids":["https://openalex.org/I102134673"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5020200003","display_name":"Simon McIntosh\u2010Smith","orcid":"https://orcid.org/0000-0002-5312-0378"},"institutions":[{"id":"https://openalex.org/I36234482","display_name":"University of Bristol","ror":"https://ror.org/0524sp257","country_code":"GB","type":"education","lineage":["https://openalex.org/I36234482"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Simon Mcintosh-Smith","raw_affiliation_strings":["School of Computer Science, University of Bristol, United Kingdom"],"affiliations":[{"raw_affiliation_string":"School of Computer Science, University of Bristol, United Kingdom","institution_ids":["https://openalex.org/I36234482"]}]}],"institutions":[],"countries_distinct_count":3,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5048181168"],"corresponding_institution_ids":["https://openalex.org/I36234482"],"apc_list":null,"apc_paid":null,"fwci":0.2536,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.4720695,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":91,"max":95},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"11"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T12292","display_name":"Graph Theory and Algorithms","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1707","display_name":"Computer Vision and Pattern Recognition"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T12292","display_name":"Graph Theory and Algorithms","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1707","display_name":"Computer Vision and Pattern Recognition"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9984999895095825,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12326","display_name":"Network Packet Processing and Optimization","score":0.9926000237464905,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/toolchain","display_name":"Toolchain","score":0.912266731262207},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8783407211303711},{"id":"https://openalex.org/keywords/stratix","display_name":"Stratix","score":0.7372007966041565},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.659721851348877},{"id":"https://openalex.org/keywords/scalability","display_name":"Scalability","score":0.6463747620582581},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.6278999447822571},{"id":"https://openalex.org/keywords/reconfigurability","display_name":"Reconfigurability","score":0.5165969133377075},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4271708130836487},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.42341890931129456},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3441605567932129},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.15756258368492126},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.12760886549949646}],"concepts":[{"id":"https://openalex.org/C2777062904","wikidata":"https://www.wikidata.org/wiki/Q545406","display_name":"Toolchain","level":3,"score":0.912266731262207},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8783407211303711},{"id":"https://openalex.org/C2776277307","wikidata":"https://www.wikidata.org/wiki/Q22074755","display_name":"Stratix","level":3,"score":0.7372007966041565},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.659721851348877},{"id":"https://openalex.org/C48044578","wikidata":"https://www.wikidata.org/wiki/Q727490","display_name":"Scalability","level":2,"score":0.6463747620582581},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6278999447822571},{"id":"https://openalex.org/C2780149590","wikidata":"https://www.wikidata.org/wiki/Q7302742","display_name":"Reconfigurability","level":2,"score":0.5165969133377075},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4271708130836487},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.42341890931129456},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3441605567932129},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.15756258368492126},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.12760886549949646}],"mesh":[],"locations_count":3,"locations":[{"id":"doi:10.1145/3648115.3648134","is_oa":true,"landing_page_url":"https://doi.org/10.1145/3648115.3648134","pdf_url":null,"source":null,"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 12th International Workshop on OpenCL and SYCL","raw_type":"proceedings-article"},{"id":"pmh:oai:research-information.bris.ac.uk:openaire/84d071db-64d5-43f7-afcf-47e0e741105d","is_oa":true,"landing_page_url":"https://research-information.bris.ac.uk/en/publications/84d071db-64d5-43f7-afcf-47e0e741105d","pdf_url":null,"source":{"id":"https://openalex.org/S7407055359","display_name":"Explore Bristol Research","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"Olgu, K, Kenter, T, Nunez-Yanez, J & Mcintosh-Smith, S 2024, Optimisation and Evaluation of Breadth First Search with oneAPI/SYCL on Intel FPGAs : From Describing Algorithms to Describing Architectures. in Proceedings of International Workshop on OpenCL and SYCL, IWOCL 2024., 6, ACM International Conference Proceeding Series, Association for Computing Machinery, pp. 1-11. https://doi.org/10.1145/3648115.3648134","raw_type":"contributionToPeriodical"},{"id":"pmh:oai:research-information.bris.ac.uk:publications/84d071db-64d5-43f7-afcf-47e0e741105d","is_oa":true,"landing_page_url":"https://hdl.handle.net/1983/84d071db-64d5-43f7-afcf-47e0e741105d","pdf_url":null,"source":{"id":"https://openalex.org/S7407055359","display_name":"Explore Bristol Research","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"Olgu, K, Kenter, T, Nunez-Yanez, J & Mcintosh-Smith, S 2024, Optimisation and Evaluation of Breadth First Search with oneAPI/SYCL on Intel FPGAs : From Describing Algorithms to Describing Architectures. in Proceedings of International Workshop on OpenCL and SYCL, IWOCL 2024., 6, ACM International Conference Proceeding Series, Association for Computing Machinery, pp. 1-11. https://doi.org/10.1145/3648115.3648134","raw_type":"contributionToPeriodical"}],"best_oa_location":{"id":"doi:10.1145/3648115.3648134","is_oa":true,"landing_page_url":"https://doi.org/10.1145/3648115.3648134","pdf_url":null,"source":null,"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 12th International Workshop on OpenCL and SYCL","raw_type":"proceedings-article"},"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":16,"referenced_works":["https://openalex.org/W1649501036","https://openalex.org/W2523378841","https://openalex.org/W2946606012","https://openalex.org/W2969746782","https://openalex.org/W2973152414","https://openalex.org/W3004241985","https://openalex.org/W3093480422","https://openalex.org/W3132871189","https://openalex.org/W4206836072","https://openalex.org/W4245683599","https://openalex.org/W4313484668","https://openalex.org/W4321637306","https://openalex.org/W4362706711","https://openalex.org/W4383749696","https://openalex.org/W4384705427","https://openalex.org/W4384833498"],"related_works":["https://openalex.org/W2159103767","https://openalex.org/W1509155667","https://openalex.org/W2518118925","https://openalex.org/W3208151864","https://openalex.org/W1564576805","https://openalex.org/W1508867949","https://openalex.org/W3166559827","https://openalex.org/W4312455642","https://openalex.org/W2056115800","https://openalex.org/W4254372399"],"abstract_inverted_index":{"FPGAs":[0],"are":[1],"often":[2],"used":[3],"in":[4,25,35,76,87,139,142,168],"scientific":[5],"fields":[6],"to":[7,12,53,95,116],"process":[8],"graph":[9],"algorithms":[10,22],"due":[11],"their":[13],"energy":[14],"efficiency,":[15],"reconfigurability,":[16],"and":[17,30,99,111,145,179],"fine-grained":[18,109,146],"parallelism.":[19],"However,":[20,105],"these":[21],"face":[23],"challenges":[24],"memory":[26,102],"access":[27],"patterns,":[28],"scalability,":[29],"programmability.":[31,55],"The":[32,72,152],"SYCL2020":[33,44],"implementation":[34,73,154],"the":[36,59,68,83,88,130],"Intel":[37,69],"oneAPI":[38,70],"toolchain":[39],"supports":[40],"FPGA":[41,66],"targets":[42],"alongside":[43,91],"features":[45],"like":[46],"modern":[47],"C++":[48],"with":[49,67,108,161,182],"a":[50,183],"single-source":[51],"offloading":[52],"improve":[54,100],"This":[56],"study":[57],"analysed":[58],"Breadth-First":[60],"Search":[61],"algorithm":[62],"on":[63,159],"Stratix":[64],"10":[65,169],"toolchain.":[71],"was":[74,113,155],"done":[75],"two":[77],"phases.":[78],"At":[79],"first,":[80],"we":[81,133],"applied":[82],"typical":[84],"optimisations":[85],"proposed":[86],"official":[89],"guidelines":[90],"an":[92],"automatic":[93],"cache":[94],"achieve":[96],"proper":[97],"pipelining":[98],"random":[101],"accesses":[103],"performance.":[104],"limitations":[106],"occurred":[107],"parallelism,":[110],"it":[112],"competitive":[114],"only":[115],"some":[117],"related":[118],"work":[119],"that":[120],"utilised":[121],"hardware-description":[122],"languages":[123],"or":[124,158],"established":[125],"high-level":[126],"synthesis":[127],"tools.":[128],"For":[129],"second":[131,153],"phase,":[132],"added":[134],"bit-level":[135],"representations":[136],"of":[137,171,186],"data":[138,150],"memory,":[140,144],"banking":[141],"on-chip":[143],"control":[147],"over":[148],"parallel":[149],"streams.":[151],"generally":[156],"superior":[157],"par":[160],"all":[162],"compared":[163],"designs,":[164],"outperforming":[165],"other":[166],"works":[167],"out":[170],"15":[172],"tested":[173],"datasets,":[174,181],"including":[175],"various":[176],"synthetic":[177],"RMAT":[178],"real-world":[180],"peak":[184],"performance":[185],"1021":[187],"MTEPS.":[188]},"counts_by_year":[{"year":2025,"cited_by_count":1}],"updated_date":"2026-03-20T23:20:44.827607","created_date":"2025-10-10T00:00:00"}