{"id":"https://openalex.org/W4399658288","doi":"https://doi.org/10.1145/3641584.3641801","title":"Implementation of a continuous high-speed data acquisition system based on FPGA","display_name":"Implementation of a continuous high-speed data acquisition system based on FPGA","publication_year":2023,"publication_date":"2023-09-22","ids":{"openalex":"https://openalex.org/W4399658288","doi":"https://doi.org/10.1145/3641584.3641801"},"language":"en","primary_location":{"id":"doi:10.1145/3641584.3641801","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3641584.3641801","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2023 6th International Conference on Artificial Intelligence and Pattern Recognition (AIPR)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5055246406","display_name":"Zhifei Dong","orcid":"https://orcid.org/0009-0008-0901-9038"},"institutions":[{"id":"https://openalex.org/I4210136859","display_name":"Xi\u2019an University of Posts and Telecommunications","ror":"https://ror.org/04jn0td46","country_code":"CN","type":"education","lineage":["https://openalex.org/I4210136859"]}],"countries":["CN"],"is_corresponding":true,"raw_author_name":"Zhifei Dong","raw_affiliation_strings":["Xi'an University of Posts &amp; Telecommunications, China"],"affiliations":[{"raw_affiliation_string":"Xi'an University of Posts &amp; Telecommunications, China","institution_ids":["https://openalex.org/I4210136859"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5065010997","display_name":"\u5049\u9298 \u4f55","orcid":"https://orcid.org/0009-0000-0093-6616"},"institutions":[{"id":"https://openalex.org/I4210136859","display_name":"Xi\u2019an University of Posts and Telecommunications","ror":"https://ror.org/04jn0td46","country_code":"CN","type":"education","lineage":["https://openalex.org/I4210136859"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Wei He","raw_affiliation_strings":["Xi'an University of Posts &amp; Telecommunications, China"],"affiliations":[{"raw_affiliation_string":"Xi'an University of Posts &amp; Telecommunications, China","institution_ids":["https://openalex.org/I4210136859"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5108943144","display_name":"Yuji Wang","orcid":"https://orcid.org/0009-0004-8034-8767"},"institutions":[{"id":"https://openalex.org/I4210136859","display_name":"Xi\u2019an University of Posts and Telecommunications","ror":"https://ror.org/04jn0td46","country_code":"CN","type":"education","lineage":["https://openalex.org/I4210136859"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Yuji Wang","raw_affiliation_strings":["Xi'an University of Posts &amp; Telecommunications, China"],"affiliations":[{"raw_affiliation_string":"Xi'an University of Posts &amp; Telecommunications, China","institution_ids":["https://openalex.org/I4210136859"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5042395066","display_name":"J.J. Liu","orcid":"https://orcid.org/0009-0003-5158-9687"},"institutions":[{"id":"https://openalex.org/I4210136859","display_name":"Xi\u2019an University of Posts and Telecommunications","ror":"https://ror.org/04jn0td46","country_code":"CN","type":"education","lineage":["https://openalex.org/I4210136859"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Jiangnan Liu","raw_affiliation_strings":["Xi'an University of Posts &amp; Telecommunications, China"],"affiliations":[{"raw_affiliation_string":"Xi'an University of Posts &amp; Telecommunications, China","institution_ids":["https://openalex.org/I4210136859"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5052459444","display_name":"Kun He","orcid":"https://orcid.org/0000-0001-9467-1304"},"institutions":[{"id":"https://openalex.org/I4210136859","display_name":"Xi\u2019an University of Posts and Telecommunications","ror":"https://ror.org/04jn0td46","country_code":"CN","type":"education","lineage":["https://openalex.org/I4210136859"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Kun He","raw_affiliation_strings":["Xi'an University of Posts &amp; Telecommunications, China"],"affiliations":[{"raw_affiliation_string":"Xi'an University of Posts &amp; Telecommunications, China","institution_ids":["https://openalex.org/I4210136859"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5055246406"],"corresponding_institution_ids":["https://openalex.org/I4210136859"],"apc_list":null,"apc_paid":null,"fwci":0.3769,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.63387161,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":95},"biblio":{"volume":null,"issue":null,"first_page":"1440","last_page":"1445"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T12941","display_name":"Embedded Systems and FPGA Design","score":0.1923999935388565,"subfield":{"id":"https://openalex.org/subfields/2207","display_name":"Control and Systems Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T12941","display_name":"Embedded Systems and FPGA Design","score":0.1923999935388565,"subfield":{"id":"https://openalex.org/subfields/2207","display_name":"Control and Systems Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T13292","display_name":"Embedded Systems and FPGA Applications","score":0.14659999310970306,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T13420","display_name":"Arduino and IoT Applications","score":0.034299999475479126,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.8424025774002075},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7233182191848755},{"id":"https://openalex.org/keywords/data-acquisition","display_name":"Data acquisition","score":0.5650153756141663},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.45790621638298035},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3804974853992462},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.21489888429641724}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.8424025774002075},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7233182191848755},{"id":"https://openalex.org/C163985040","wikidata":"https://www.wikidata.org/wiki/Q1172399","display_name":"Data acquisition","level":2,"score":0.5650153756141663},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.45790621638298035},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3804974853992462},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.21489888429641724}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/3641584.3641801","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3641584.3641801","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2023 6th International Conference on Artificial Intelligence and Pattern Recognition (AIPR)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","score":0.41999998688697815,"display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":9,"referenced_works":["https://openalex.org/W2555861474","https://openalex.org/W2898425293","https://openalex.org/W2907492846","https://openalex.org/W2957311908","https://openalex.org/W3102054685","https://openalex.org/W3102740456","https://openalex.org/W4296391430","https://openalex.org/W6600140940","https://openalex.org/W6603514168"],"related_works":["https://openalex.org/W2350916690","https://openalex.org/W2096844293","https://openalex.org/W2363944576","https://openalex.org/W2351041855","https://openalex.org/W3174413644","https://openalex.org/W2351458975","https://openalex.org/W2570254841","https://openalex.org/W2510354731","https://openalex.org/W2054430068","https://openalex.org/W2994099990"],"abstract_inverted_index":{"In":[0,83],"order":[1],"to":[2,41,56,76],"meet":[3],"the":[4,53,67,72,77,80,95,100,104,121,131],"requirements":[5],"of":[6,34],"high-speed":[7,14],"and":[8,24,36,61,70,97,130],"high-reliability":[9],"data":[10,15,44,48,58,92,106,123,128,132],"acquisition":[11,16,45,124],"(DAQ),":[12],"a":[13],"system":[17,125],"based":[18],"on":[19],"FPGA":[20,37,51,78],"with":[21],"high":[22],"performance":[23],"low":[25],"cost":[26],"is":[27,39,52,107],"implemented":[28],"in":[29,110],"this":[30],"study.":[31],"A":[32],"combination":[33],"embedded":[35],"technology":[38],"introduced":[40],"achieve":[42],"continuous":[43],"without":[46],"any":[47],"loss.":[49],"The":[50,63,116],"core":[54],"device":[55],"control":[57],"acquisition,":[59],"transfer,":[60],"storage.":[62],"ADC":[64,96],"chip":[65],"samples":[66],"analog":[68],"signal":[69,75],"transfers":[71],"converted":[73],"digital":[74],"using":[79],"LVDS":[81],"protocol.":[82],"addition,":[84],"Scatter":[85],"Gather":[86],"Direct":[87],"Register":[88],"Access":[89],"(SGDMA)":[90],"realizes":[91],"transfer":[93,133],"between":[94],"SDRAM":[98,112],"for":[99,113],"acquired":[101,105],"data.":[102],"Finally,":[103],"temporarily":[108],"stored":[109],"DDR3":[111],"further":[114],"manipulation.":[115],"experimental":[117],"results":[118],"show":[119],"that":[120],"designed":[122],"can":[126],"acquire":[127],"correctly,":[129],"rate":[134],"exceeds":[135],"1.6":[136],"Gbps.":[137]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2024,"cited_by_count":1}],"updated_date":"2026-03-03T08:47:05.690250","created_date":"2025-10-10T00:00:00"}
