{"id":"https://openalex.org/W4387933363","doi":"https://doi.org/10.1145/3629523","title":"FlowPix: Accelerating Image Processing Pipelines on an FPGA Overlay using a Domain Specific Compiler","display_name":"FlowPix: Accelerating Image Processing Pipelines on an FPGA Overlay using a Domain Specific Compiler","publication_year":2023,"publication_date":"2023-10-25","ids":{"openalex":"https://openalex.org/W4387933363","doi":"https://doi.org/10.1145/3629523"},"language":"en","primary_location":{"id":"doi:10.1145/3629523","is_oa":true,"landing_page_url":"https://doi.org/10.1145/3629523","pdf_url":"https://dl.acm.org/doi/pdf/10.1145/3629523","source":{"id":"https://openalex.org/S26056741","display_name":"ACM Transactions on Architecture and Code Optimization","issn_l":"1544-3566","issn":["1544-3566","1544-3973"],"is_oa":true,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319798","host_organization_name":"Association for Computing Machinery","host_organization_lineage":["https://openalex.org/P4310319798"],"host_organization_lineage_names":["Association for Computing Machinery"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"ACM Transactions on Architecture and Code Optimization","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"diamond","oa_url":"https://dl.acm.org/doi/pdf/10.1145/3629523","any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5064037179","display_name":"Ziaul Choudhury","orcid":"https://orcid.org/0000-0001-9019-0239"},"institutions":[{"id":"https://openalex.org/I64189192","display_name":"International Institute of Information Technology, Hyderabad","ror":"https://ror.org/05f11g639","country_code":"IN","type":"education","lineage":["https://openalex.org/I64189192"]}],"countries":["IN"],"is_corresponding":true,"raw_author_name":"Ziaul Choudhury","raw_affiliation_strings":["Computer Systems Group, International Institute of Information Technology Hyderabad, India"],"affiliations":[{"raw_affiliation_string":"Computer Systems Group, International Institute of Information Technology Hyderabad, India","institution_ids":["https://openalex.org/I64189192"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5085995931","display_name":"A. Gulati","orcid":"https://orcid.org/0009-0005-2666-079X"},"institutions":[{"id":"https://openalex.org/I64189192","display_name":"International Institute of Information Technology, Hyderabad","ror":"https://ror.org/05f11g639","country_code":"IN","type":"education","lineage":["https://openalex.org/I64189192"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Anish Gulati","raw_affiliation_strings":["Computer Systems Group, International Institute of Information Technology Hyderabad, India"],"affiliations":[{"raw_affiliation_string":"Computer Systems Group, International Institute of Information Technology Hyderabad, India","institution_ids":["https://openalex.org/I64189192"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5008869877","display_name":"Suresh Purini","orcid":"https://orcid.org/0000-0001-5094-995X"},"institutions":[{"id":"https://openalex.org/I64189192","display_name":"International Institute of Information Technology, Hyderabad","ror":"https://ror.org/05f11g639","country_code":"IN","type":"education","lineage":["https://openalex.org/I64189192"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Suresh Purini","raw_affiliation_strings":["Computer Systems Group, International Institute of Information Technology Hyderabad, India"],"affiliations":[{"raw_affiliation_string":"Computer Systems Group, International Institute of Information Technology Hyderabad, India","institution_ids":["https://openalex.org/I64189192"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5064037179"],"corresponding_institution_ids":["https://openalex.org/I64189192"],"apc_list":null,"apc_paid":null,"fwci":0.9075,"has_fulltext":true,"cited_by_count":3,"citation_normalized_percentile":{"value":0.72456652,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":96},"biblio":{"volume":"20","issue":"4","first_page":"1","last_page":"25"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9987000226974487,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9973999857902527,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8565032482147217},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.6719815731048584},{"id":"https://openalex.org/keywords/control-reconfiguration","display_name":"Control reconfiguration","score":0.5497999787330627},{"id":"https://openalex.org/keywords/compiler","display_name":"Compiler","score":0.5229283571243286},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5199012160301208},{"id":"https://openalex.org/keywords/reconfigurable-computing","display_name":"Reconfigurable computing","score":0.49813413619995117},{"id":"https://openalex.org/keywords/design-space-exploration","display_name":"Design space exploration","score":0.4616588056087494},{"id":"https://openalex.org/keywords/image-processing","display_name":"Image processing","score":0.428707480430603},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.40192392468452454},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3821214437484741},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.34957826137542725},{"id":"https://openalex.org/keywords/image","display_name":"Image (mathematics)","score":0.1533682644367218},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.14459779858589172},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.10768046975135803}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8565032482147217},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6719815731048584},{"id":"https://openalex.org/C119701452","wikidata":"https://www.wikidata.org/wiki/Q5165881","display_name":"Control reconfiguration","level":2,"score":0.5497999787330627},{"id":"https://openalex.org/C169590947","wikidata":"https://www.wikidata.org/wiki/Q47506","display_name":"Compiler","level":2,"score":0.5229283571243286},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5199012160301208},{"id":"https://openalex.org/C142962650","wikidata":"https://www.wikidata.org/wiki/Q240838","display_name":"Reconfigurable computing","level":3,"score":0.49813413619995117},{"id":"https://openalex.org/C2776221188","wikidata":"https://www.wikidata.org/wiki/Q21072556","display_name":"Design space exploration","level":2,"score":0.4616588056087494},{"id":"https://openalex.org/C9417928","wikidata":"https://www.wikidata.org/wiki/Q1070689","display_name":"Image processing","level":3,"score":0.428707480430603},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.40192392468452454},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3821214437484741},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.34957826137542725},{"id":"https://openalex.org/C115961682","wikidata":"https://www.wikidata.org/wiki/Q860623","display_name":"Image (mathematics)","level":2,"score":0.1533682644367218},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.14459779858589172},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.10768046975135803}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/3629523","is_oa":true,"landing_page_url":"https://doi.org/10.1145/3629523","pdf_url":"https://dl.acm.org/doi/pdf/10.1145/3629523","source":{"id":"https://openalex.org/S26056741","display_name":"ACM Transactions on Architecture and Code Optimization","issn_l":"1544-3566","issn":["1544-3566","1544-3973"],"is_oa":true,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319798","host_organization_name":"Association for Computing Machinery","host_organization_lineage":["https://openalex.org/P4310319798"],"host_organization_lineage_names":["Association for Computing Machinery"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"ACM Transactions on Architecture and Code Optimization","raw_type":"journal-article"}],"best_oa_location":{"id":"doi:10.1145/3629523","is_oa":true,"landing_page_url":"https://doi.org/10.1145/3629523","pdf_url":"https://dl.acm.org/doi/pdf/10.1145/3629523","source":{"id":"https://openalex.org/S26056741","display_name":"ACM Transactions on Architecture and Code Optimization","issn_l":"1544-3566","issn":["1544-3566","1544-3973"],"is_oa":true,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319798","host_organization_name":"Association for Computing Machinery","host_organization_lineage":["https://openalex.org/P4310319798"],"host_organization_lineage_names":["Association for Computing Machinery"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"ACM Transactions on Architecture and Code Optimization","raw_type":"journal-article"},"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":true,"grobid_xml":true},"content_urls":{"pdf":"https://content.openalex.org/works/W4387933363.pdf","grobid_xml":"https://content.openalex.org/works/W4387933363.grobid-xml"},"referenced_works_count":37,"referenced_works":["https://openalex.org/W1502650061","https://openalex.org/W1964471912","https://openalex.org/W1973948335","https://openalex.org/W1980208272","https://openalex.org/W1983394510","https://openalex.org/W1987163471","https://openalex.org/W2014206209","https://openalex.org/W2021944457","https://openalex.org/W2034248530","https://openalex.org/W2084069479","https://openalex.org/W2094998159","https://openalex.org/W2097959379","https://openalex.org/W2106962797","https://openalex.org/W2120431055","https://openalex.org/W2130425801","https://openalex.org/W2140321074","https://openalex.org/W2166029537","https://openalex.org/W2466242877","https://openalex.org/W2517689844","https://openalex.org/W2524530727","https://openalex.org/W2544002786","https://openalex.org/W2771210328","https://openalex.org/W2780077279","https://openalex.org/W2906720721","https://openalex.org/W3006236305","https://openalex.org/W3007436455","https://openalex.org/W3033664232","https://openalex.org/W3042501387","https://openalex.org/W4210258659","https://openalex.org/W4224265992","https://openalex.org/W4225426816","https://openalex.org/W4241765343","https://openalex.org/W4245440340","https://openalex.org/W4247199268","https://openalex.org/W4251309856","https://openalex.org/W4255653201","https://openalex.org/W6959847839"],"related_works":["https://openalex.org/W2135053878","https://openalex.org/W2941434274","https://openalex.org/W4249632163","https://openalex.org/W2797161794","https://openalex.org/W2096938998","https://openalex.org/W1760305469","https://openalex.org/W2103526090","https://openalex.org/W2340647897","https://openalex.org/W2808484818","https://openalex.org/W1574948540"],"abstract_inverted_index":{"The":[0,255,283,312],"exponential":[1],"performance":[2,42,387],"growth":[3],"guaranteed":[4],"by":[5,45],"Moore\u2019s":[6],"law":[7],"has":[8,116,228],"started":[9],"to":[10,32,39,56,102,117,122,141,168,188,216,251,319,349,358,368],"taper":[11],"in":[12,119,163,231,242,258,266,297,352,361,413],"recent":[13],"years.":[14],"At":[15],"the":[16,33,41,82,114,124,127,164,209,232,298,362,374,385,414],"same":[17],"time,":[18],"emerging":[19],"applications":[20],"like":[21,96,174,322,333],"image":[22,235,280],"processing":[23,236,239,281],"demand":[24],"heavy":[25],"computational":[26,295],"performance.":[27],"These":[28],"factors":[29],"inevitably":[30],"lead":[31],"emergence":[34],"of":[35,63,72,81,221,234,377,402,408],"domain-specific":[36],"accelerators":[37],"(DSA)":[38],"fill":[40],"void":[43],"left":[44],"conventional":[46],"architectures.":[47],"FPGAs":[48,77],"are":[49,107,166,194,198,286],"rapidly":[50],"evolving":[51],"towards":[52,88,110],"becoming":[53],"an":[54,260,398],"alternative":[55],"custom":[57],"ASICs":[58],"for":[59,182,279],"designing":[60,259],"DSAs":[61,155,199],"because":[62],"their":[64],"low":[65],"power":[66],"consumption":[67,392],"and":[68,85,113,135,206,244,335,381,389],"a":[69,148,201,218,273,294,309,356],"higher":[70],"degree":[71],"parallelism.":[73],"DSA":[74],"design":[75,103],"on":[76,208,308,405],"requires":[78,178],"careful":[79],"calibration":[80],"FPGA":[83,104,180,210,363,382],"compute":[84],"memory":[86],"resources":[87],"achieving":[89],"optimal":[90],"throughput.":[91],"Hardware":[92],"Descriptive":[93],"Languages":[94,133],"(HDL)":[95],"Verilog":[97],"have":[98,137,153],"been":[99,138,229],"traditionally":[100],"used":[101,140],"hardware.":[105,342],"HDLs":[106,145],"not":[108],"geared":[109],"any":[111,370],"domain,":[112],"user":[115],"put":[118],"much":[120],"effort":[121],"describe":[123],"hardware":[125,191,378],"at":[126],"register":[128],"transfer":[129],"level.":[130],"Domain":[131],"Specific":[132],"(DSLs)":[134],"compilers":[136],"recently":[139],"weave":[142],"together":[143],"handwritten":[144],"templates":[146,170],"targeting":[147,159],"specific":[149],"domain.":[150],"Recent":[151],"efforts":[152],"designed":[154],"with":[156,290,354],"image-processing":[157,261,304],"DSLs":[158],"FPGAs.":[160],"Image":[161,238],"computations":[162,222],"DSL":[165,284],"lowered":[167],"pre-existing":[169],"or":[171],"lower-level":[172],"languages":[173],"HLS-C.":[175],"This":[176,270],"approach":[177],"expensive":[179],"re-flashing":[181,383],"every":[183],"new":[184],"workload.":[185],"In":[186],"contrast":[187],"this":[189],"fixed-function":[190,341],"approach,":[192],"overlays":[193],"gaining":[195],"traction.":[196],"Overlays":[197],"resembling":[200],"processor,":[202],"which":[203],"is":[204,213,263],"synthesized":[205],"flashed":[207],"once":[211],"but":[212],"flexible":[214],"enough":[215],"process":[217],"broad":[219],"class":[220],"through":[223],"soft":[224],"reconfiguration.":[225],"Less":[226],"work":[227],"reported":[230],"context":[233],"overlays.":[237],"algorithms":[240],"vary":[241],"size":[243],"shape,":[245],"ranging":[246],"from":[247,315],"simple":[248,316],"blurring":[249],"operations":[250,318],"complex":[252,320],"pyramid":[253],"systems.":[254],"primary":[256],"challenge":[257],"overlay":[262,275],"maintaining":[264],"flexibility":[265],"mapping":[267],"different":[268],"algorithms.":[269],"paper":[271],"proposes":[272],"DSL-based":[274],"accelerator":[276],"called":[277],"FlowPix":[278,307,328,396],"applications.":[282],"programs":[285],"expressed":[287],"as":[288],"pipelines,":[289],"each":[291],"stage":[292],"representing":[293],"step":[296],"overall":[299],"algorithm.":[300],"We":[301,326],"implement":[302],"15":[303],"benchmarks":[305,313],"using":[306],"Virtex-7-690t":[310],"FPGA.":[311],"range":[314],"blur":[317],"pipelines":[321],"Lucas-Kande":[323],"optical":[324],"flow.":[325],"compare":[327],"against":[329],"existing":[330],"DSL-to-FPGA":[331],"frameworks":[332],"Hetero-Halide":[334],"Vitis":[336],"Vision":[337],"library":[338],"that":[339,393],"generate":[340],"On":[343],"most":[344],"benchmarks,":[345],"we":[346,394],"see":[347],"up":[348],"25%":[350],"degradation":[351],"latency":[353],"approximately":[355],"1.7x":[357],"2x":[359],"increase":[360],"LUT":[364],"consumption.":[365],"Our":[366],"ability":[367],"execute":[369],"benchmark":[371],"without":[372],"incurring":[373],"high":[375],"costs":[376],"synthesis,":[379],"place-and-route,":[380],"justifies":[384],"slight":[386],"loss":[388],"increased":[390],"resource":[391],"experience.":[395],"achieves":[397],"average":[399],"frame":[400],"rate":[401],"170":[403],"FPS":[404],"HD":[406],"frames":[407],"1920":[409],"\u00d7":[410],"1080":[411],"pixels":[412],"implemented":[415],"benchmarks.":[416]},"counts_by_year":[{"year":2025,"cited_by_count":2},{"year":2024,"cited_by_count":1}],"updated_date":"2026-03-27T05:58:40.876381","created_date":"2025-10-10T00:00:00"}