{"id":"https://openalex.org/W4391959065","doi":"https://doi.org/10.1145/3627535.3638497","title":"Memory Bounds for Concurrent Bounded Queues","display_name":"Memory Bounds for Concurrent Bounded Queues","publication_year":2024,"publication_date":"2024-02-20","ids":{"openalex":"https://openalex.org/W4391959065","doi":"https://doi.org/10.1145/3627535.3638497"},"language":"en","primary_location":{"id":"doi:10.1145/3627535.3638497","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3627535.3638497","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 29th ACM SIGPLAN Annual Symposium on Principles and Practice of Parallel Programming","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5069723237","display_name":"Vitaly Aksenov","orcid":"https://orcid.org/0000-0001-9134-5490"},"institutions":[{"id":"https://openalex.org/I180825142","display_name":"City, University of London","ror":"https://ror.org/04489at23","country_code":"GB","type":"education","lineage":["https://openalex.org/I124357947","https://openalex.org/I180825142"]}],"countries":["GB"],"is_corresponding":true,"raw_author_name":"Vitaly Aksenov","raw_affiliation_strings":["City, University of London, London, United Kingdom"],"raw_orcid":"https://orcid.org/0000-0001-9134-5490","affiliations":[{"raw_affiliation_string":"City, University of London, London, United Kingdom","institution_ids":["https://openalex.org/I180825142"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5047006729","display_name":"Nikita Koval","orcid":"https://orcid.org/0000-0002-1260-4616"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Nikita Koval","raw_affiliation_strings":["JetBrains, Amsterdam, Netherlands"],"raw_orcid":"https://orcid.org/0000-0002-1260-4616","affiliations":[{"raw_affiliation_string":"JetBrains, Amsterdam, Netherlands","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101714664","display_name":"Petr Kuznetsov","orcid":"https://orcid.org/0000-0003-1148-1228"},"institutions":[{"id":"https://openalex.org/I12356871","display_name":"T\u00e9l\u00e9com Paris","ror":"https://ror.org/01naq7912","country_code":"FR","type":"education","lineage":["https://openalex.org/I12356871","https://openalex.org/I205703379","https://openalex.org/I4210145102"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"Petr Kuznetsov","raw_affiliation_strings":["Telecom Paris, Institut Polytechnique Paris, Paris, France"],"raw_orcid":"https://orcid.org/0000-0003-1148-1228","affiliations":[{"raw_affiliation_string":"Telecom Paris, Institut Polytechnique Paris, Paris, France","institution_ids":["https://openalex.org/I12356871"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5067587616","display_name":"Anton Paramonov","orcid":"https://orcid.org/0009-0000-0760-8746"},"institutions":[{"id":"https://openalex.org/I5124864","display_name":"\u00c9cole Polytechnique F\u00e9d\u00e9rale de Lausanne","ror":"https://ror.org/02s376052","country_code":"CH","type":"education","lineage":["https://openalex.org/I2799323385","https://openalex.org/I5124864"]}],"countries":["CH"],"is_corresponding":false,"raw_author_name":"Anton Paramonov","raw_affiliation_strings":["EPFL, Lausanne, Switzerland"],"raw_orcid":"https://orcid.org/0009-0000-0760-8746","affiliations":[{"raw_affiliation_string":"EPFL, Lausanne, Switzerland","institution_ids":["https://openalex.org/I5124864"]}]}],"institutions":[],"countries_distinct_count":3,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5069723237"],"corresponding_institution_ids":["https://openalex.org/I180825142"],"apc_list":null,"apc_paid":null,"fwci":0.3347,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.53910864,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":91,"max":95},"biblio":{"volume":null,"issue":null,"first_page":"188","last_page":"199"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10772","display_name":"Distributed systems and fault tolerance","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10772","display_name":"Distributed systems and fault tolerance","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10933","display_name":"Real-Time Systems Scheduling","score":0.9983999729156494,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9980000257492065,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8063317537307739},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.7178665399551392},{"id":"https://openalex.org/keywords/interleaved-memory","display_name":"Interleaved memory","score":0.7081205248832703},{"id":"https://openalex.org/keywords/registered-memory","display_name":"Registered memory","score":0.6048632860183716},{"id":"https://openalex.org/keywords/memory-map","display_name":"Memory map","score":0.5515565276145935},{"id":"https://openalex.org/keywords/concurrent-data-structure","display_name":"Concurrent data structure","score":0.5313485264778137},{"id":"https://openalex.org/keywords/uniform-memory-access","display_name":"Uniform memory access","score":0.5169236063957214},{"id":"https://openalex.org/keywords/memory-management","display_name":"Memory management","score":0.5074898600578308},{"id":"https://openalex.org/keywords/shared-memory","display_name":"Shared memory","score":0.5039824843406677},{"id":"https://openalex.org/keywords/flat-memory-model","display_name":"Flat memory model","score":0.4653874933719635},{"id":"https://openalex.org/keywords/cpu-cache","display_name":"CPU cache","score":0.44263768196105957},{"id":"https://openalex.org/keywords/synchronization","display_name":"Synchronization (alternating current)","score":0.4421631693840027},{"id":"https://openalex.org/keywords/cache-only-memory-architecture","display_name":"Cache-only memory architecture","score":0.43406370282173157},{"id":"https://openalex.org/keywords/overhead","display_name":"Overhead (engineering)","score":0.4127548336982727},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.37141314148902893},{"id":"https://openalex.org/keywords/concurrency","display_name":"Concurrency","score":0.3373674750328064},{"id":"https://openalex.org/keywords/overlay","display_name":"Overlay","score":0.3176223635673523},{"id":"https://openalex.org/keywords/distributed-computing","display_name":"Distributed computing","score":0.2665291428565979},{"id":"https://openalex.org/keywords/cache-coloring","display_name":"Cache coloring","score":0.2272438406944275},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.21848222613334656},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.0970408022403717}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8063317537307739},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.7178665399551392},{"id":"https://openalex.org/C63511323","wikidata":"https://www.wikidata.org/wiki/Q908936","display_name":"Interleaved memory","level":4,"score":0.7081205248832703},{"id":"https://openalex.org/C93446704","wikidata":"https://www.wikidata.org/wiki/Q449328","display_name":"Registered memory","level":3,"score":0.6048632860183716},{"id":"https://openalex.org/C74426580","wikidata":"https://www.wikidata.org/wiki/Q719484","display_name":"Memory map","level":3,"score":0.5515565276145935},{"id":"https://openalex.org/C203222032","wikidata":"https://www.wikidata.org/wiki/Q5159104","display_name":"Concurrent data structure","level":3,"score":0.5313485264778137},{"id":"https://openalex.org/C51290061","wikidata":"https://www.wikidata.org/wiki/Q1936765","display_name":"Uniform memory access","level":4,"score":0.5169236063957214},{"id":"https://openalex.org/C176649486","wikidata":"https://www.wikidata.org/wiki/Q2308807","display_name":"Memory management","level":3,"score":0.5074898600578308},{"id":"https://openalex.org/C133875982","wikidata":"https://www.wikidata.org/wiki/Q764810","display_name":"Shared memory","level":2,"score":0.5039824843406677},{"id":"https://openalex.org/C57863822","wikidata":"https://www.wikidata.org/wiki/Q905488","display_name":"Flat memory model","level":4,"score":0.4653874933719635},{"id":"https://openalex.org/C189783530","wikidata":"https://www.wikidata.org/wiki/Q352090","display_name":"CPU cache","level":3,"score":0.44263768196105957},{"id":"https://openalex.org/C2778562939","wikidata":"https://www.wikidata.org/wiki/Q1298791","display_name":"Synchronization (alternating current)","level":3,"score":0.4421631693840027},{"id":"https://openalex.org/C3720319","wikidata":"https://www.wikidata.org/wiki/Q5015937","display_name":"Cache-only memory architecture","level":5,"score":0.43406370282173157},{"id":"https://openalex.org/C2779960059","wikidata":"https://www.wikidata.org/wiki/Q7113681","display_name":"Overhead (engineering)","level":2,"score":0.4127548336982727},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.37141314148902893},{"id":"https://openalex.org/C193702766","wikidata":"https://www.wikidata.org/wiki/Q1414548","display_name":"Concurrency","level":2,"score":0.3373674750328064},{"id":"https://openalex.org/C136085584","wikidata":"https://www.wikidata.org/wiki/Q910289","display_name":"Overlay","level":2,"score":0.3176223635673523},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.2665291428565979},{"id":"https://openalex.org/C201148951","wikidata":"https://www.wikidata.org/wiki/Q5015976","display_name":"Cache coloring","level":4,"score":0.2272438406944275},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.21848222613334656},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.0970408022403717},{"id":"https://openalex.org/C127162648","wikidata":"https://www.wikidata.org/wiki/Q16858953","display_name":"Channel (broadcasting)","level":2,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1145/3627535.3638497","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3627535.3638497","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 29th ACM SIGPLAN Annual Symposium on Principles and Practice of Parallel Programming","raw_type":"proceedings-article"},{"id":"pmh:oai:openaccess.city.ac.uk:36665","is_oa":false,"landing_page_url":"https://openaccess.city.ac.uk/view/creators_id/vitaly=2Eaksenov.html>","pdf_url":null,"source":{"id":"https://openalex.org/S4306401940","display_name":"City Research Online (City University London)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I180825142","host_organization_name":"City, University of London","host_organization_lineage":["https://openalex.org/I180825142"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"acceptedVersion","is_accepted":true,"is_published":false,"raw_source_name":null,"raw_type":"PeerReviewed"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":17,"referenced_works":["https://openalex.org/W1540179969","https://openalex.org/W1550253372","https://openalex.org/W1551823290","https://openalex.org/W1885809555","https://openalex.org/W1931014159","https://openalex.org/W1966054908","https://openalex.org/W2015956262","https://openalex.org/W2030205622","https://openalex.org/W2062200908","https://openalex.org/W2101939036","https://openalex.org/W2417507107","https://openalex.org/W2551733116","https://openalex.org/W2968116716","https://openalex.org/W3015821333","https://openalex.org/W3089033718","https://openalex.org/W4321446125","https://openalex.org/W4321466316"],"related_works":["https://openalex.org/W3048967625","https://openalex.org/W3021597805","https://openalex.org/W4317815260","https://openalex.org/W4321458411","https://openalex.org/W2934889147","https://openalex.org/W2096506606","https://openalex.org/W2043352873","https://openalex.org/W1975698617","https://openalex.org/W2565280077","https://openalex.org/W2168550483"],"abstract_inverted_index":{"Concurrent":[0],"data":[1],"structures":[2],"often":[3],"require":[4],"additional":[5,24],"memory":[6,14,40,50],"for":[7,15],"handling":[8],"synchronization":[9],"issues":[10],"in":[11,43],"addition":[12],"to":[13],"storing":[16],"elements.":[17],"Depending":[18],"on":[19],"the":[20,37],"amount":[21],"of":[22],"this":[23],"memory,":[25],"implementations":[26],"can":[27],"be":[28],"more":[29],"or":[30],"less":[31],"memory-friendly.":[32],"A":[33],"memory-optimal":[34],"implementation":[35],"enjoys":[36],"minimal":[38],"possible":[39],"overhead,":[41],"which,":[42],"practice,":[44],"reduces":[45],"cache":[46],"misses":[47],"and":[48],"unnecessary":[49],"reclamation.":[51]},"counts_by_year":[{"year":2025,"cited_by_count":1}],"updated_date":"2026-04-29T09:16:38.111599","created_date":"2025-10-10T00:00:00"}