{"id":"https://openalex.org/W4399886260","doi":"https://doi.org/10.1145/3625223.3649266","title":"The Impact of Heterogeneous Logic on Adders and Multipliers in VTR","display_name":"The Impact of Heterogeneous Logic on Adders and Multipliers in VTR","publication_year":2023,"publication_date":"2023-09-21","ids":{"openalex":"https://openalex.org/W4399886260","doi":"https://doi.org/10.1145/3625223.3649266"},"language":"en","primary_location":{"id":"doi:10.1145/3625223.3649266","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3625223.3649266","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 34th International Workshop on Rapid System Prototyping","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5099339955","display_name":"Navid Jafarof","orcid":"https://orcid.org/0009-0000-7504-1243"},"institutions":[{"id":"https://openalex.org/I106938459","display_name":"University of New Brunswick","ror":"https://ror.org/05nkf0n29","country_code":"CA","type":"education","lineage":["https://openalex.org/I106938459"]}],"countries":["CA"],"is_corresponding":true,"raw_author_name":"Navid Jafarof","raw_affiliation_strings":["Faculty of Computer Science, University of New Brunswick, Fredericton, Canada"],"raw_orcid":"https://orcid.org/0009-0000-7504-1243","affiliations":[{"raw_affiliation_string":"Faculty of Computer Science, University of New Brunswick, Fredericton, Canada","institution_ids":["https://openalex.org/I106938459"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5067605823","display_name":"Kenneth B. Kent","orcid":"https://orcid.org/0000-0003-2764-823X"},"institutions":[{"id":"https://openalex.org/I106938459","display_name":"University of New Brunswick","ror":"https://ror.org/05nkf0n29","country_code":"CA","type":"education","lineage":["https://openalex.org/I106938459"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Kenneth B. Kent","raw_affiliation_strings":["Faculty of Computer Science, University of New Brunswick, Fredericton, Canada"],"raw_orcid":"https://orcid.org/0000-0003-2764-823X","affiliations":[{"raw_affiliation_string":"Faculty of Computer Science, University of New Brunswick, Fredericton, Canada","institution_ids":["https://openalex.org/I106938459"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5099339955"],"corresponding_institution_ids":["https://openalex.org/I106938459"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.21798389,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"7"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9988999962806702,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7155222296714783},{"id":"https://openalex.org/keywords/adder","display_name":"Adder","score":0.6659029722213745},{"id":"https://openalex.org/keywords/arithmetic","display_name":"Arithmetic","score":0.562286376953125},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.4711032509803772},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.44313135743141174},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.39042115211486816},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.32862725853919983},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.19190186262130737},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.14848801493644714},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.07643356919288635},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.07289683818817139}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7155222296714783},{"id":"https://openalex.org/C164620267","wikidata":"https://www.wikidata.org/wiki/Q376953","display_name":"Adder","level":3,"score":0.6659029722213745},{"id":"https://openalex.org/C94375191","wikidata":"https://www.wikidata.org/wiki/Q11205","display_name":"Arithmetic","level":1,"score":0.562286376953125},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.4711032509803772},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.44313135743141174},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.39042115211486816},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.32862725853919983},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.19190186262130737},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.14848801493644714},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.07643356919288635},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.07289683818817139}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/3625223.3649266","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3625223.3649266","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 34th International Workshop on Rapid System Prototyping","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":8,"referenced_works":["https://openalex.org/W73549669","https://openalex.org/W1523051745","https://openalex.org/W2005602803","https://openalex.org/W2138383740","https://openalex.org/W2139637699","https://openalex.org/W2168493238","https://openalex.org/W3033033241","https://openalex.org/W4232341571"],"related_works":["https://openalex.org/W2013839957","https://openalex.org/W3196607417","https://openalex.org/W2098419840","https://openalex.org/W1966764473","https://openalex.org/W2789349722","https://openalex.org/W1985308002","https://openalex.org/W2121963733","https://openalex.org/W1977171228","https://openalex.org/W2059422871","https://openalex.org/W2766377030"],"abstract_inverted_index":{"This":[0,44],"paper":[1],"presents":[2],"an":[3],"extension":[4],"of":[5,18,33,54,81,85,122,125],"the":[6,16,29,42,49,82,111,120],"Verilog-to-Routing":[7],"(VTR)":[8],"Computer-Aided":[9],"Design":[10],"(CAD)":[11],"tool,":[12],"focusing":[13],"specifically":[14],"on":[15],"utilization":[17,84],"heterogeneous":[19,30],"logic":[20,31,66,126],"for":[21,62,118],"both":[22],"multipliers":[23],"and":[24,40,59,64,71,102,114],"adders.":[25],"We":[26],"build":[27],"upon":[28],"implementation":[32],"adders":[34],"in":[35,52,100,105,127],"VTR":[36],"by":[37],"addressing":[38],"bugs":[39],"refining":[41],"implementation.":[43],"research":[45],"aims":[46],"to":[47],"uncover":[48],"optimal":[50],"configuration":[51],"terms":[53],"critical":[55],"path":[56],"delay":[57],"(CPD)":[58],"device":[60,106],"area":[61],"hard":[63,87],"soft":[65,89],"implementations":[67],"within":[68],"different":[69,123],"architectures":[70],"designs.":[72],"Our":[73],"findings":[74],"show":[75],"that":[76],"a":[77],"balanced":[78],"approach,":[79],"instead":[80],"exclusive":[83],"either":[86],"or":[88],"logic,":[90],"can":[91],"yield":[92],"superior":[93],"results.":[94],"Extensive":[95],"testing":[96],"reveals":[97],"significant":[98],"improvements":[99],"speed":[101],"potential":[103],"reductions":[104],"size.":[107],"The":[108],"results":[109],"validate":[110],"implementation's":[112],"success":[113],"suggest":[115],"future":[116],"directions":[117],"enhancing":[119],"use":[121],"types":[124],"VTR.":[128]},"counts_by_year":[],"updated_date":"2026-03-27T05:58:40.876381","created_date":"2025-10-10T00:00:00"}
