{"id":"https://openalex.org/W4388561528","doi":"https://doi.org/10.1145/3624062.3624542","title":"Altis-SYCL: Migrating Altis Benchmarking Suite from CUDA to SYCL for GPUs and FPGAs","display_name":"Altis-SYCL: Migrating Altis Benchmarking Suite from CUDA to SYCL for GPUs and FPGAs","publication_year":2023,"publication_date":"2023-11-10","ids":{"openalex":"https://openalex.org/W4388561528","doi":"https://doi.org/10.1145/3624062.3624542"},"language":"en","primary_location":{"id":"doi:10.1145/3624062.3624542","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3624062.3624542","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the SC '23 Workshops of the International Conference on High Performance Computing, Network, Storage, and Analysis","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5093236266","display_name":"Christoph Weckert","orcid":"https://orcid.org/0009-0000-5399-1379"},"institutions":[{"id":"https://openalex.org/I31512782","display_name":"Technische Universit\u00e4t Darmstadt","ror":"https://ror.org/05n911h24","country_code":"DE","type":"education","lineage":["https://openalex.org/I31512782"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Christoph Weckert","raw_affiliation_strings":["Technical University of Darmstadt, Germany"],"raw_orcid":"https://orcid.org/0009-0000-5399-1379","affiliations":[{"raw_affiliation_string":"Technical University of Darmstadt, Germany","institution_ids":["https://openalex.org/I31512782"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5037721262","display_name":"Leonardo Solis-Vasquez","orcid":"https://orcid.org/0000-0001-6896-9879"},"institutions":[{"id":"https://openalex.org/I31512782","display_name":"Technische Universit\u00e4t Darmstadt","ror":"https://ror.org/05n911h24","country_code":"DE","type":"education","lineage":["https://openalex.org/I31512782"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Leonardo Solis-Vasquez","raw_affiliation_strings":["Technical University of Darmstadt, Germany"],"raw_orcid":"https://orcid.org/0000-0001-6896-9879","affiliations":[{"raw_affiliation_string":"Technical University of Darmstadt, Germany","institution_ids":["https://openalex.org/I31512782"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5010007635","display_name":"Julian Oppermann","orcid":"https://orcid.org/0000-0002-8073-720X"},"institutions":[{"id":"https://openalex.org/I31512782","display_name":"Technische Universit\u00e4t Darmstadt","ror":"https://ror.org/05n911h24","country_code":"DE","type":"education","lineage":["https://openalex.org/I31512782"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Julian Oppermann","raw_affiliation_strings":["Technical University of Darmstadt, Germany"],"raw_orcid":"https://orcid.org/0000-0002-8073-720X","affiliations":[{"raw_affiliation_string":"Technical University of Darmstadt, Germany","institution_ids":["https://openalex.org/I31512782"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5047000315","display_name":"Andreas Koch","orcid":"https://orcid.org/0000-0002-1164-3082"},"institutions":[{"id":"https://openalex.org/I31512782","display_name":"Technische Universit\u00e4t Darmstadt","ror":"https://ror.org/05n911h24","country_code":"DE","type":"education","lineage":["https://openalex.org/I31512782"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Andreas Koch","raw_affiliation_strings":["Technical University of Darmstadt, Germany"],"raw_orcid":"https://orcid.org/0000-0002-1164-3082","affiliations":[{"raw_affiliation_string":"Technical University of Darmstadt, Germany","institution_ids":["https://openalex.org/I31512782"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5088706361","display_name":"Oliver Sinnen","orcid":"https://orcid.org/0000-0002-1550-7416"},"institutions":[{"id":"https://openalex.org/I154130895","display_name":"University of Auckland","ror":"https://ror.org/03b94tp07","country_code":"NZ","type":"education","lineage":["https://openalex.org/I154130895"]}],"countries":["NZ"],"is_corresponding":false,"raw_author_name":"Oliver Sinnen","raw_affiliation_strings":["University of Auckland, New Zealand"],"raw_orcid":"https://orcid.org/0000-0002-1550-7416","affiliations":[{"raw_affiliation_string":"University of Auckland, New Zealand","institution_ids":["https://openalex.org/I154130895"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":5,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":1.4417,"has_fulltext":false,"cited_by_count":5,"citation_normalized_percentile":{"value":0.81520913,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":95,"max":97},"biblio":{"volume":null,"issue":null,"first_page":"547","last_page":"555"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.991599977016449,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12326","display_name":"Network Packet Processing and Optimization","score":0.9883999824523926,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/suite","display_name":"Suite","score":0.7458646893501282},{"id":"https://openalex.org/keywords/cuda","display_name":"CUDA","score":0.7249900698661804},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7238807082176208},{"id":"https://openalex.org/keywords/benchmark","display_name":"Benchmark (surveying)","score":0.6941044330596924},{"id":"https://openalex.org/keywords/benchmarking","display_name":"Benchmarking","score":0.6551252603530884},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5701621174812317},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.5463942289352417},{"id":"https://openalex.org/keywords/leverage","display_name":"Leverage (statistics)","score":0.4483717978000641},{"id":"https://openalex.org/keywords/general-purpose-computing-on-graphics-processing-units","display_name":"General-purpose computing on graphics processing units","score":0.42812249064445496},{"id":"https://openalex.org/keywords/code","display_name":"Code (set theory)","score":0.4208359718322754},{"id":"https://openalex.org/keywords/code-refactoring","display_name":"Code refactoring","score":0.4104490876197815},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.34379857778549194},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.33810722827911377},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.31743741035461426},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.21892514824867249},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.14535081386566162},{"id":"https://openalex.org/keywords/graphics","display_name":"Graphics","score":0.07099306583404541},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.06908425688743591}],"concepts":[{"id":"https://openalex.org/C79581498","wikidata":"https://www.wikidata.org/wiki/Q1367530","display_name":"Suite","level":2,"score":0.7458646893501282},{"id":"https://openalex.org/C2778119891","wikidata":"https://www.wikidata.org/wiki/Q477690","display_name":"CUDA","level":2,"score":0.7249900698661804},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7238807082176208},{"id":"https://openalex.org/C185798385","wikidata":"https://www.wikidata.org/wiki/Q1161707","display_name":"Benchmark (surveying)","level":2,"score":0.6941044330596924},{"id":"https://openalex.org/C86251818","wikidata":"https://www.wikidata.org/wiki/Q816754","display_name":"Benchmarking","level":2,"score":0.6551252603530884},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5701621174812317},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.5463942289352417},{"id":"https://openalex.org/C153083717","wikidata":"https://www.wikidata.org/wiki/Q6535263","display_name":"Leverage (statistics)","level":2,"score":0.4483717978000641},{"id":"https://openalex.org/C50630238","wikidata":"https://www.wikidata.org/wiki/Q971505","display_name":"General-purpose computing on graphics processing units","level":3,"score":0.42812249064445496},{"id":"https://openalex.org/C2776760102","wikidata":"https://www.wikidata.org/wiki/Q5139990","display_name":"Code (set theory)","level":3,"score":0.4208359718322754},{"id":"https://openalex.org/C152752567","wikidata":"https://www.wikidata.org/wiki/Q116877","display_name":"Code refactoring","level":3,"score":0.4104490876197815},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.34379857778549194},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.33810722827911377},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.31743741035461426},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.21892514824867249},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.14535081386566162},{"id":"https://openalex.org/C21442007","wikidata":"https://www.wikidata.org/wiki/Q1027879","display_name":"Graphics","level":2,"score":0.07099306583404541},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.06908425688743591},{"id":"https://openalex.org/C95457728","wikidata":"https://www.wikidata.org/wiki/Q309","display_name":"History","level":0,"score":0.0},{"id":"https://openalex.org/C144133560","wikidata":"https://www.wikidata.org/wiki/Q4830453","display_name":"Business","level":0,"score":0.0},{"id":"https://openalex.org/C162853370","wikidata":"https://www.wikidata.org/wiki/Q39809","display_name":"Marketing","level":1,"score":0.0},{"id":"https://openalex.org/C13280743","wikidata":"https://www.wikidata.org/wiki/Q131089","display_name":"Geodesy","level":1,"score":0.0},{"id":"https://openalex.org/C205649164","wikidata":"https://www.wikidata.org/wiki/Q1071","display_name":"Geography","level":0,"score":0.0},{"id":"https://openalex.org/C166957645","wikidata":"https://www.wikidata.org/wiki/Q23498","display_name":"Archaeology","level":1,"score":0.0},{"id":"https://openalex.org/C177264268","wikidata":"https://www.wikidata.org/wiki/Q1514741","display_name":"Set (abstract data type)","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/3624062.3624542","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3624062.3624542","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the SC '23 Workshops of the International Conference on High Performance Computing, Network, Storage, and Analysis","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.5099999904632568,"id":"https://metadata.un.org/sdg/10","display_name":"Reduced inequalities"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":13,"referenced_works":["https://openalex.org/W2080592089","https://openalex.org/W2149234156","https://openalex.org/W3097287637","https://openalex.org/W3121665290","https://openalex.org/W3174757733","https://openalex.org/W3198401590","https://openalex.org/W4200005713","https://openalex.org/W4206836072","https://openalex.org/W4225548362","https://openalex.org/W4289827486","https://openalex.org/W4308090268","https://openalex.org/W4308090288","https://openalex.org/W4386026126"],"related_works":["https://openalex.org/W1963859303","https://openalex.org/W2364044215","https://openalex.org/W2389600408","https://openalex.org/W240129890","https://openalex.org/W3048701459","https://openalex.org/W2149078538","https://openalex.org/W2080146221","https://openalex.org/W2370314112","https://openalex.org/W1912958759","https://openalex.org/W2792081825"],"abstract_inverted_index":{"In":[0,74],"this":[1,75],"work,":[2],"we":[3,19,77],"introduce":[4],"Altis-SYCL,":[5,18],"a":[6],"benchmark":[7,37],"suite":[8,38],"based":[9],"on":[10,101,119],"SYCL":[11,61],"for":[12,108],"GPUs":[13,68],"and":[14,41,48,69,92,104,107],"FPGAs.":[15,73],"For":[16],"developing":[17],"leverage":[20],"the":[21,33,56,59,79,88],"oneAPI":[22],"heterogeneous":[23],"programming":[24],"framework":[25],"in":[26],"two":[27],"consecutive":[28],"steps:":[29],"1)":[30],"by":[31,50],"using":[32],"modern":[34],"Altis":[35],"GPGPU":[36],"as":[39,84,86,128],"baseline":[40],"migrating":[42],"it":[43],"from":[44],"CUDA":[45],"to":[46,54],"SYCL,":[47],"2)":[49],"exploring":[51],"several":[52],"techniques":[53],"optimize":[55],"performance":[57,96],"of":[58,97],"resulting":[60],"code.":[62],"Our":[63],"migration-and-optimization":[64],"methodology":[65],"starts":[66],"targeting":[67],"progressively":[70],"moves":[71],"towards":[72],"process,":[76],"discuss":[78],"differences":[80],"between":[81],"device-specific":[82],"strategies":[83],"well":[85],"detailing":[87],"required":[89],"code":[90,125],"refactoring":[91],"optimization":[93],"efforts.":[94],"The":[95,123],"Altis-SYCL":[98],"was":[99],"evaluated":[100],"Stratix":[102],"10":[103],"Agilex":[105],"FPGAs,":[106],"some":[109],"applications,":[110],"their":[111],"execution":[112],"runtimes":[113],"were":[114],"competitive":[115],"with":[116],"those":[117],"achieved":[118],"latest":[120],"high-end":[121],"GPUs.":[122],"corresponding":[124],"is":[126],"released":[127],"open":[129],"source":[130],"under:":[131],"https://github.com/esa-tu-darmstadt/altis_sycl.":[132]},"counts_by_year":[{"year":2025,"cited_by_count":2},{"year":2024,"cited_by_count":3}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}