{"id":"https://openalex.org/W4388561639","doi":"https://doi.org/10.1145/3624062.3624540","title":"Enabling Communication with FPGA-based Network-attached Accelerators for HPC Workloads","display_name":"Enabling Communication with FPGA-based Network-attached Accelerators for HPC Workloads","publication_year":2023,"publication_date":"2023-11-10","ids":{"openalex":"https://openalex.org/W4388561639","doi":"https://doi.org/10.1145/3624062.3624540"},"language":"en","primary_location":{"id":"doi:10.1145/3624062.3624540","is_oa":true,"landing_page_url":"https://doi.org/10.1145/3624062.3624540","pdf_url":"https://dl.acm.org/doi/pdf/10.1145/3624062.3624540","source":null,"license":"cc-by-nc-nd","license_id":"https://openalex.org/licenses/cc-by-nc-nd","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the SC '23 Workshops of the International Conference on High Performance Computing, Network, Storage, and Analysis","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"gold","oa_url":"https://dl.acm.org/doi/pdf/10.1145/3624062.3624540","any_repository_has_fulltext":null},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5022420494","display_name":"Steffen Christgau","orcid":"https://orcid.org/0000-0002-8702-8422"},"institutions":[{"id":"https://openalex.org/I195893171","display_name":"Zuse Institute Berlin","ror":"https://ror.org/02eva5865","country_code":"DE","type":"facility","lineage":["https://openalex.org/I195893171"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Steffen Christgau","raw_affiliation_strings":["Supercomputing Department, Zuse Institute Berlin, Germany"],"raw_orcid":"https://orcid.org/0000-0002-8702-8422","affiliations":[{"raw_affiliation_string":"Supercomputing Department, Zuse Institute Berlin, Germany","institution_ids":["https://openalex.org/I195893171"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5093236293","display_name":"Dylan Everingham","orcid":"https://orcid.org/0009-0003-8847-6221"},"institutions":[{"id":"https://openalex.org/I195893171","display_name":"Zuse Institute Berlin","ror":"https://ror.org/02eva5865","country_code":"DE","type":"facility","lineage":["https://openalex.org/I195893171"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Dylan Everingham","raw_affiliation_strings":["Supercomputing Department, Zuse Institute Berlin, Germany"],"raw_orcid":"https://orcid.org/0009-0003-8847-6221","affiliations":[{"raw_affiliation_string":"Supercomputing Department, Zuse Institute Berlin, Germany","institution_ids":["https://openalex.org/I195893171"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5044376967","display_name":"Florian Mikolajczak","orcid":"https://orcid.org/0009-0004-9884-9383"},"institutions":[{"id":"https://openalex.org/I176453806","display_name":"University of Potsdam","ror":"https://ror.org/03bnmw459","country_code":"DE","type":"education","lineage":["https://openalex.org/I176453806"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Florian Mikolajczak","raw_affiliation_strings":["Institute of Computer Science, University of Potsdam, Germany"],"raw_orcid":"https://orcid.org/0009-0004-9884-9383","affiliations":[{"raw_affiliation_string":"Institute of Computer Science, University of Potsdam, Germany","institution_ids":["https://openalex.org/I176453806"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5041087021","display_name":"Niklas Schelten","orcid":"https://orcid.org/0000-0002-6597-4928"},"institutions":[{"id":"https://openalex.org/I2800274787","display_name":"Fraunhofer Institute for Telecommunications, Heinrich Hertz Institute","ror":"https://ror.org/02tbr6331","country_code":"DE","type":"facility","lineage":["https://openalex.org/I2800274787","https://openalex.org/I4923324"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Niklas Schelten","raw_affiliation_strings":["Embedded Systems Group, Fraunhofer Heinrich Hertz Institute, Germany"],"raw_orcid":"https://orcid.org/0000-0002-6597-4928","affiliations":[{"raw_affiliation_string":"Embedded Systems Group, Fraunhofer Heinrich Hertz Institute, Germany","institution_ids":["https://openalex.org/I2800274787"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5044374029","display_name":"Bettina Schnor","orcid":"https://orcid.org/0000-0001-7369-8057"},"institutions":[{"id":"https://openalex.org/I176453806","display_name":"University of Potsdam","ror":"https://ror.org/03bnmw459","country_code":"DE","type":"education","lineage":["https://openalex.org/I176453806"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Bettina Schnor","raw_affiliation_strings":["Institute of Computer Science, University of Potsdam, Germany"],"raw_orcid":"https://orcid.org/0000-0001-7369-8057","affiliations":[{"raw_affiliation_string":"Institute of Computer Science, University of Potsdam, Germany","institution_ids":["https://openalex.org/I176453806"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5040315133","display_name":"Max Schroetter","orcid":"https://orcid.org/0000-0003-0788-5983"},"institutions":[{"id":"https://openalex.org/I176453806","display_name":"University of Potsdam","ror":"https://ror.org/03bnmw459","country_code":"DE","type":"education","lineage":["https://openalex.org/I176453806"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Max Schroetter","raw_affiliation_strings":["Institute of Computer Science, University of Potsdam, Germany"],"raw_orcid":"https://orcid.org/0000-0003-0788-5983","affiliations":[{"raw_affiliation_string":"Institute of Computer Science, University of Potsdam, Germany","institution_ids":["https://openalex.org/I176453806"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5038698717","display_name":"Benno Stabernack","orcid":"https://orcid.org/0000-0002-6654-1606"},"institutions":[{"id":"https://openalex.org/I176453806","display_name":"University of Potsdam","ror":"https://ror.org/03bnmw459","country_code":"DE","type":"education","lineage":["https://openalex.org/I176453806"]},{"id":"https://openalex.org/I2800274787","display_name":"Fraunhofer Institute for Telecommunications, Heinrich Hertz Institute","ror":"https://ror.org/02tbr6331","country_code":"DE","type":"facility","lineage":["https://openalex.org/I2800274787","https://openalex.org/I4923324"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Benno Stabernack","raw_affiliation_strings":["Embedded Systems Group, Fraunhofer Heinrich Hertz Institute, Germany and Embedded Systems Architectures for Signalprocessing, University of Potsdam, Germany"],"raw_orcid":"https://orcid.org/0000-0002-6654-1606","affiliations":[{"raw_affiliation_string":"Embedded Systems Group, Fraunhofer Heinrich Hertz Institute, Germany and Embedded Systems Architectures for Signalprocessing, University of Potsdam, Germany","institution_ids":["https://openalex.org/I176453806","https://openalex.org/I2800274787"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5040177395","display_name":"Fritjof Steinert","orcid":"https://orcid.org/0000-0002-8733-3064"},"institutions":[{"id":"https://openalex.org/I176453806","display_name":"University of Potsdam","ror":"https://ror.org/03bnmw459","country_code":"DE","type":"education","lineage":["https://openalex.org/I176453806"]},{"id":"https://openalex.org/I2800274787","display_name":"Fraunhofer Institute for Telecommunications, Heinrich Hertz Institute","ror":"https://ror.org/02tbr6331","country_code":"DE","type":"facility","lineage":["https://openalex.org/I2800274787","https://openalex.org/I4923324"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Fritjof Steinert","raw_affiliation_strings":["Embedded Systems Group, Fraunhofer Heinrich Hertz Institute, Germany and Embedded Systems Architectures for Signalprocessing, University of Potsdam, Germany"],"raw_orcid":"https://orcid.org/0000-0002-8733-3064","affiliations":[{"raw_affiliation_string":"Embedded Systems Group, Fraunhofer Heinrich Hertz Institute, Germany and Embedded Systems Architectures for Signalprocessing, University of Potsdam, Germany","institution_ids":["https://openalex.org/I176453806","https://openalex.org/I2800274787"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":true,"cited_by_count":1,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"530","last_page":"538"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/remote-direct-memory-access","display_name":"Remote direct memory access","score":0.9244412779808044},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.788948655128479},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7366594672203064},{"id":"https://openalex.org/keywords/infiniband","display_name":"InfiniBand","score":0.657946765422821},{"id":"https://openalex.org/keywords/ethernet","display_name":"Ethernet","score":0.6293898224830627},{"id":"https://openalex.org/keywords/pci-express","display_name":"PCI Express","score":0.6151601076126099},{"id":"https://openalex.org/keywords/interface","display_name":"Interface (matter)","score":0.510438859462738},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.48417502641677856},{"id":"https://openalex.org/keywords/supercomputer","display_name":"Supercomputer","score":0.47394517064094543},{"id":"https://openalex.org/keywords/flexibility","display_name":"Flexibility (engineering)","score":0.4693499505519867},{"id":"https://openalex.org/keywords/data-center","display_name":"Data center","score":0.4683270752429962},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.4605094790458679},{"id":"https://openalex.org/keywords/stack","display_name":"Stack (abstract data type)","score":0.4249148368835449},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.35636115074157715},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.35396647453308105}],"concepts":[{"id":"https://openalex.org/C130795937","wikidata":"https://www.wikidata.org/wiki/Q2561570","display_name":"Remote direct memory access","level":2,"score":0.9244412779808044},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.788948655128479},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7366594672203064},{"id":"https://openalex.org/C2781030343","wikidata":"https://www.wikidata.org/wiki/Q922437","display_name":"InfiniBand","level":2,"score":0.657946765422821},{"id":"https://openalex.org/C172173386","wikidata":"https://www.wikidata.org/wiki/Q79984","display_name":"Ethernet","level":2,"score":0.6293898224830627},{"id":"https://openalex.org/C64270927","wikidata":"https://www.wikidata.org/wiki/Q206924","display_name":"PCI Express","level":3,"score":0.6151601076126099},{"id":"https://openalex.org/C113843644","wikidata":"https://www.wikidata.org/wiki/Q901882","display_name":"Interface (matter)","level":4,"score":0.510438859462738},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.48417502641677856},{"id":"https://openalex.org/C83283714","wikidata":"https://www.wikidata.org/wiki/Q121117","display_name":"Supercomputer","level":2,"score":0.47394517064094543},{"id":"https://openalex.org/C2780598303","wikidata":"https://www.wikidata.org/wiki/Q65921492","display_name":"Flexibility (engineering)","level":2,"score":0.4693499505519867},{"id":"https://openalex.org/C153740404","wikidata":"https://www.wikidata.org/wiki/Q671224","display_name":"Data center","level":2,"score":0.4683270752429962},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.4605094790458679},{"id":"https://openalex.org/C9395851","wikidata":"https://www.wikidata.org/wiki/Q177929","display_name":"Stack (abstract data type)","level":2,"score":0.4249148368835449},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.35636115074157715},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.35396647453308105},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C129307140","wikidata":"https://www.wikidata.org/wiki/Q6795880","display_name":"Maximum bubble pressure method","level":3,"score":0.0},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0},{"id":"https://openalex.org/C157915830","wikidata":"https://www.wikidata.org/wiki/Q2928001","display_name":"Bubble","level":2,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1145/3624062.3624540","is_oa":true,"landing_page_url":"https://doi.org/10.1145/3624062.3624540","pdf_url":"https://dl.acm.org/doi/pdf/10.1145/3624062.3624540","source":null,"license":"cc-by-nc-nd","license_id":"https://openalex.org/licenses/cc-by-nc-nd","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the SC '23 Workshops of the International Conference on High Performance Computing, Network, Storage, and Analysis","raw_type":"proceedings-article"},{"id":"pmh:oai:publica.fraunhofer.de:publica/513758","is_oa":false,"landing_page_url":"https://publica.fraunhofer.de/handle/publica/513758","pdf_url":null,"source":{"id":"https://openalex.org/S4306400318","display_name":"Fraunhofer-Publica (Fraunhofer-Gesellschaft)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I4923324","host_organization_name":"Fraunhofer-Gesellschaft","host_organization_lineage":["https://openalex.org/I4923324"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"conference paper"}],"best_oa_location":{"id":"doi:10.1145/3624062.3624540","is_oa":true,"landing_page_url":"https://doi.org/10.1145/3624062.3624540","pdf_url":"https://dl.acm.org/doi/pdf/10.1145/3624062.3624540","source":null,"license":"cc-by-nc-nd","license_id":"https://openalex.org/licenses/cc-by-nc-nd","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the SC '23 Workshops of the International Conference on High Performance Computing, Network, Storage, and Analysis","raw_type":"proceedings-article"},"sustainable_development_goals":[{"display_name":"Affordable and clean energy","score":0.8999999761581421,"id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[{"id":"https://openalex.org/F4320321114","display_name":"Bundesministerium f\u00fcr Bildung und Forschung","ror":"https://ror.org/04pz7b180"}],"has_content":{"pdf":true,"grobid_xml":true},"content_urls":{"pdf":"https://content.openalex.org/works/W4388561639.pdf","grobid_xml":"https://content.openalex.org/works/W4388561639.grobid-xml"},"referenced_works_count":31,"referenced_works":["https://openalex.org/W1979229768","https://openalex.org/W2005574683","https://openalex.org/W2037639500","https://openalex.org/W2128827681","https://openalex.org/W2129120770","https://openalex.org/W2475840367","https://openalex.org/W2614193845","https://openalex.org/W2894590528","https://openalex.org/W2944140784","https://openalex.org/W2949799853","https://openalex.org/W2950768554","https://openalex.org/W2972179099","https://openalex.org/W2983413335","https://openalex.org/W2985435314","https://openalex.org/W3020134715","https://openalex.org/W3034991763","https://openalex.org/W3035430964","https://openalex.org/W3092526199","https://openalex.org/W3093796669","https://openalex.org/W3101861725","https://openalex.org/W3106016107","https://openalex.org/W3107015997","https://openalex.org/W3121665290","https://openalex.org/W3128237131","https://openalex.org/W3162045814","https://openalex.org/W4288086140","https://openalex.org/W4312190975","https://openalex.org/W4319309389","https://openalex.org/W4362706711","https://openalex.org/W4381327316","https://openalex.org/W4389582761"],"related_works":["https://openalex.org/W1978254186","https://openalex.org/W4245217724","https://openalex.org/W4390917331","https://openalex.org/W4253931064","https://openalex.org/W1984788566","https://openalex.org/W1966974913","https://openalex.org/W2937592512","https://openalex.org/W1901618855","https://openalex.org/W2132218766","https://openalex.org/W2097029373"],"abstract_inverted_index":{"The":[0,133],"use":[1,79],"of":[2,19,25,35,49,80,123],"stand-alone,":[3],"network-coupled":[4],"Field":[5],"Programmable":[6],"Gate":[7],"Array":[8],"(FPGA)":[9],"accelerators":[10],"is":[11,43,119],"intended":[12],"to":[13,88,149],"significantly":[14],"increase":[15],"the":[16,33,36,41,46,50,64,69,73,77,90,96,124,150],"energy":[17,66],"efficiency":[18],"HPC":[20,26,37,97],"applications":[21],"and":[22,40,61,68,111,144],"thus":[23],"also":[24],"data":[27,38,51,98],"centers.":[28],"A":[29,100],"loose":[30],"coupling":[31],"between":[32],"nodes":[34,60],"center":[39],"FPGAs":[42],"established":[44],"through":[45,72],"high-speed":[47],"network":[48,74],"center.":[52,99],"This":[53,82],"allows":[54],"greater":[55],"flexibility":[56,71],"in":[57],"combining":[58],"different":[59],"accelerators.":[62],"Both":[63],"resulting":[65],"savings":[67],"increased":[70],"connection,":[75],"enable":[76],"economical":[78],"FPGAs.":[81],"work":[83],"presents":[84],"a":[85,112],"communication":[86,131],"stack":[87],"integrate":[89],"so-called":[91],"Network-attached":[92],"Accelerator":[93],"(NAA)":[94],"into":[95],"low-level":[101],"Remote":[102,114],"Direct":[103],"Memory":[104],"Access":[105],"(RDMA)":[106],"Application":[107],"Programming":[108],"Interface":[109],"(API)":[110],"high-level":[113],"Procedure":[115],"Call":[116],"(RPC)":[117],"API":[118],"designed":[120],"on":[121],"top":[122],"RDMA":[125],"over":[126,136],"Converged":[127],"Ethernet":[128],"v2":[129],"(RoCEv2)":[130],"stack.":[132],"experimental":[134],"results":[135],"100":[137],"Gbps":[138],"RoCEv2":[139],"show":[140],"that":[141],"our":[142],"design":[143],"implementation":[145],"deliver":[146],"performance":[147],"close":[148],"theoretical":[151],"maximum.":[152]},"counts_by_year":[{"year":2024,"cited_by_count":1}],"updated_date":"2026-07-22T07:51:19.307946","created_date":"2025-10-10T00:00:00"}