{"id":"https://openalex.org/W4395020645","doi":"https://doi.org/10.1145/3620665.3640428","title":"PIM-STM: Software Transactional Memory for Processing-In-Memory Systems","display_name":"PIM-STM: Software Transactional Memory for Processing-In-Memory Systems","publication_year":2024,"publication_date":"2024-04-22","ids":{"openalex":"https://openalex.org/W4395020645","doi":"https://doi.org/10.1145/3620665.3640428"},"language":"en","primary_location":{"id":"doi:10.1145/3620665.3640428","is_oa":true,"landing_page_url":"https://doi.org/10.1145/3620665.3640428","pdf_url":null,"source":null,"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 29th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 2","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"gold","oa_url":"https://doi.org/10.1145/3620665.3640428","any_repository_has_fulltext":null},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5038181221","display_name":"Andr\u00e9 Lopes","orcid":"https://orcid.org/0009-0002-8039-9033"},"institutions":[{"id":"https://openalex.org/I121345201","display_name":"Instituto de Engenharia de Sistemas e Computadores Investiga\u00e7\u00e3o e Desenvolvimento","ror":"https://ror.org/04mqy3p58","country_code":"PT","type":"nonprofit","lineage":["https://openalex.org/I121345201","https://openalex.org/I4210125590"]}],"countries":["PT"],"is_corresponding":true,"raw_author_name":"Andr\u00e9 Lopes","raw_affiliation_strings":["IST/INESC-ID, Lisbon, Portugal"],"affiliations":[{"raw_affiliation_string":"IST/INESC-ID, Lisbon, Portugal","institution_ids":["https://openalex.org/I121345201"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5070358654","display_name":"Daniel Castro","orcid":"https://orcid.org/0000-0002-7564-0454"},"institutions":[{"id":"https://openalex.org/I121345201","display_name":"Instituto de Engenharia de Sistemas e Computadores Investiga\u00e7\u00e3o e Desenvolvimento","ror":"https://ror.org/04mqy3p58","country_code":"PT","type":"nonprofit","lineage":["https://openalex.org/I121345201","https://openalex.org/I4210125590"]}],"countries":["PT"],"is_corresponding":false,"raw_author_name":"Daniel Castro","raw_affiliation_strings":["IST/INESC-ID, Lisbon, Portugal"],"affiliations":[{"raw_affiliation_string":"IST/INESC-ID, Lisbon, Portugal","institution_ids":["https://openalex.org/I121345201"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5049600349","display_name":"Paolo Romano","orcid":"https://orcid.org/0000-0001-7026-7446"},"institutions":[{"id":"https://openalex.org/I121345201","display_name":"Instituto de Engenharia de Sistemas e Computadores Investiga\u00e7\u00e3o e Desenvolvimento","ror":"https://ror.org/04mqy3p58","country_code":"PT","type":"nonprofit","lineage":["https://openalex.org/I121345201","https://openalex.org/I4210125590"]}],"countries":["PT"],"is_corresponding":false,"raw_author_name":"Paolo Romano","raw_affiliation_strings":["IST/INESC-ID, Lisbon, Portugal"],"affiliations":[{"raw_affiliation_string":"IST/INESC-ID, Lisbon, Portugal","institution_ids":["https://openalex.org/I121345201"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5038181221"],"corresponding_institution_ids":["https://openalex.org/I121345201"],"apc_list":null,"apc_paid":null,"fwci":2.922,"has_fulltext":false,"cited_by_count":8,"citation_normalized_percentile":{"value":0.91143537,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":96,"max":98},"biblio":{"volume":null,"issue":null,"first_page":"897","last_page":"911"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10772","display_name":"Distributed systems and fault tolerance","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10772","display_name":"Distributed systems and fault tolerance","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9980000257492065,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9854000210762024,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.831030011177063},{"id":"https://openalex.org/keywords/software-transactional-memory","display_name":"Software transactional memory","score":0.6554389595985413},{"id":"https://openalex.org/keywords/bottleneck","display_name":"Bottleneck","score":0.6381171941757202},{"id":"https://openalex.org/keywords/transactional-memory","display_name":"Transactional memory","score":0.5711455941200256},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5566087961196899},{"id":"https://openalex.org/keywords/dram","display_name":"Dram","score":0.549017071723938},{"id":"https://openalex.org/keywords/memory-architecture","display_name":"Memory architecture","score":0.5455247759819031},{"id":"https://openalex.org/keywords/memory-management","display_name":"Memory management","score":0.5366951823234558},{"id":"https://openalex.org/keywords/memory-map","display_name":"Memory map","score":0.53025883436203},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5011234283447266},{"id":"https://openalex.org/keywords/registered-memory","display_name":"Registered memory","score":0.4672622084617615},{"id":"https://openalex.org/keywords/interleaved-memory","display_name":"Interleaved memory","score":0.45228976011276245},{"id":"https://openalex.org/keywords/conventional-memory","display_name":"Conventional memory","score":0.4449236989021301},{"id":"https://openalex.org/keywords/transaction-processing","display_name":"Transaction processing","score":0.4258754849433899},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3795775771141052},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.3591352105140686},{"id":"https://openalex.org/keywords/overlay","display_name":"Overlay","score":0.3541370630264282},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.2442464530467987},{"id":"https://openalex.org/keywords/database-transaction","display_name":"Database transaction","score":0.16865026950836182},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.13802435994148254}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.831030011177063},{"id":"https://openalex.org/C167149655","wikidata":"https://www.wikidata.org/wiki/Q1189004","display_name":"Software transactional memory","level":4,"score":0.6554389595985413},{"id":"https://openalex.org/C2780513914","wikidata":"https://www.wikidata.org/wiki/Q18210350","display_name":"Bottleneck","level":2,"score":0.6381171941757202},{"id":"https://openalex.org/C134277064","wikidata":"https://www.wikidata.org/wiki/Q878206","display_name":"Transactional memory","level":3,"score":0.5711455941200256},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5566087961196899},{"id":"https://openalex.org/C7366592","wikidata":"https://www.wikidata.org/wiki/Q1255620","display_name":"Dram","level":2,"score":0.549017071723938},{"id":"https://openalex.org/C2779602883","wikidata":"https://www.wikidata.org/wiki/Q15544750","display_name":"Memory architecture","level":2,"score":0.5455247759819031},{"id":"https://openalex.org/C176649486","wikidata":"https://www.wikidata.org/wiki/Q2308807","display_name":"Memory management","level":3,"score":0.5366951823234558},{"id":"https://openalex.org/C74426580","wikidata":"https://www.wikidata.org/wiki/Q719484","display_name":"Memory map","level":3,"score":0.53025883436203},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5011234283447266},{"id":"https://openalex.org/C93446704","wikidata":"https://www.wikidata.org/wiki/Q449328","display_name":"Registered memory","level":3,"score":0.4672622084617615},{"id":"https://openalex.org/C63511323","wikidata":"https://www.wikidata.org/wiki/Q908936","display_name":"Interleaved memory","level":4,"score":0.45228976011276245},{"id":"https://openalex.org/C53838383","wikidata":"https://www.wikidata.org/wiki/Q541148","display_name":"Conventional memory","level":5,"score":0.4449236989021301},{"id":"https://openalex.org/C72108876","wikidata":"https://www.wikidata.org/wiki/Q844565","display_name":"Transaction processing","level":3,"score":0.4258754849433899},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3795775771141052},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.3591352105140686},{"id":"https://openalex.org/C136085584","wikidata":"https://www.wikidata.org/wiki/Q910289","display_name":"Overlay","level":2,"score":0.3541370630264282},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.2442464530467987},{"id":"https://openalex.org/C75949130","wikidata":"https://www.wikidata.org/wiki/Q848010","display_name":"Database transaction","level":2,"score":0.16865026950836182},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.13802435994148254}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/3620665.3640428","is_oa":true,"landing_page_url":"https://doi.org/10.1145/3620665.3640428","pdf_url":null,"source":null,"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 29th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 2","raw_type":"proceedings-article"}],"best_oa_location":{"id":"doi:10.1145/3620665.3640428","is_oa":true,"landing_page_url":"https://doi.org/10.1145/3620665.3640428","pdf_url":null,"source":null,"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 29th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 2","raw_type":"proceedings-article"},"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","score":0.46000000834465027,"display_name":"Affordable and clean energy"}],"awards":[{"id":"https://openalex.org/G2441341484","display_name":null,"funder_award_id":"UIDB/50021/2020","funder_id":"https://openalex.org/F4320334779","funder_display_name":"Funda\u00e7\u00e3o para a Ci\u00eancia e a Tecnologia"}],"funders":[{"id":"https://openalex.org/F4320334779","display_name":"Funda\u00e7\u00e3o para a Ci\u00eancia e a Tecnologia","ror":"https://ror.org/00snfqn58"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":44,"referenced_works":["https://openalex.org/W1542975293","https://openalex.org/W1977661221","https://openalex.org/W1988800505","https://openalex.org/W1992490313","https://openalex.org/W2008258200","https://openalex.org/W2008330181","https://openalex.org/W2009564195","https://openalex.org/W2032791226","https://openalex.org/W2061863279","https://openalex.org/W2084130915","https://openalex.org/W2094222793","https://openalex.org/W2097447543","https://openalex.org/W2105055683","https://openalex.org/W2108204150","https://openalex.org/W2113751407","https://openalex.org/W2114688360","https://openalex.org/W2122621236","https://openalex.org/W2124840905","https://openalex.org/W2128585185","https://openalex.org/W2130749812","https://openalex.org/W2132220514","https://openalex.org/W2144650313","https://openalex.org/W2149089882","https://openalex.org/W2163654949","https://openalex.org/W2272558877","https://openalex.org/W2593176800","https://openalex.org/W2728945542","https://openalex.org/W2736517506","https://openalex.org/W2808573889","https://openalex.org/W2916475468","https://openalex.org/W2920081941","https://openalex.org/W2943801410","https://openalex.org/W2950151409","https://openalex.org/W2967324946","https://openalex.org/W2971801673","https://openalex.org/W3014709850","https://openalex.org/W3159011214","https://openalex.org/W3202917172","https://openalex.org/W4242859796","https://openalex.org/W4285503912","https://openalex.org/W4289785683","https://openalex.org/W4321466371","https://openalex.org/W4387544219","https://openalex.org/W4394788044"],"related_works":["https://openalex.org/W3048967625","https://openalex.org/W2753615087","https://openalex.org/W2296275612","https://openalex.org/W4248614727","https://openalex.org/W4386793373","https://openalex.org/W1975698617","https://openalex.org/W2168550483","https://openalex.org/W2561005478","https://openalex.org/W4293159259","https://openalex.org/W2378551620"],"abstract_inverted_index":{"Processing-In-Memory":[0],"(PIM)":[1],"is":[2],"a":[3],"novel":[4],"approach":[5],"that":[6,32],"augments":[7],"existing":[8],"DRAM":[9],"memory":[10],"chips":[11],"with":[12],"lightweight":[13],"logic.":[14],"By":[15],"allowing":[16],"to":[17,20],"offload":[18],"computations":[19],"the":[21,29],"PIM":[22],"system,":[23],"this":[24],"architecture":[25],"allows":[26],"for":[27],"circumventing":[28],"data-bottleneck":[30],"problem":[31],"affects":[33],"many":[34],"modern":[35],"workloads.":[36]},"counts_by_year":[{"year":2025,"cited_by_count":3},{"year":2024,"cited_by_count":5}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
