{"id":"https://openalex.org/W4366380722","doi":"https://doi.org/10.1145/3584376.3584564","title":"Design of portable data monitor for construction machinery based on FPGA","display_name":"Design of portable data monitor for construction machinery based on FPGA","publication_year":2022,"publication_date":"2022-12-16","ids":{"openalex":"https://openalex.org/W4366380722","doi":"https://doi.org/10.1145/3584376.3584564"},"language":"en","primary_location":{"id":"doi:10.1145/3584376.3584564","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3584376.3584564","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2022 4th International Conference on Robotics, Intelligent Control and Artificial Intelligence","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5054878542","display_name":"Shugang Liu","orcid":"https://orcid.org/0000-0002-4797-4967"},"institutions":[{"id":"https://openalex.org/I121296143","display_name":"Hunan University of Science and Technology","ror":"https://ror.org/02m9vrb24","country_code":"CN","type":"education","lineage":["https://openalex.org/I121296143"]}],"countries":["CN"],"is_corresponding":true,"raw_author_name":"Shugang Liu","raw_affiliation_strings":["School of Physics and Electronic Science, Hunan University of Science and Technology, China"],"affiliations":[{"raw_affiliation_string":"School of Physics and Electronic Science, Hunan University of Science and Technology, China","institution_ids":["https://openalex.org/I121296143"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5057832454","display_name":"Weixin Nie","orcid":"https://orcid.org/0000-0002-2960-4436"},"institutions":[{"id":"https://openalex.org/I121296143","display_name":"Hunan University of Science and Technology","ror":"https://ror.org/02m9vrb24","country_code":"CN","type":"education","lineage":["https://openalex.org/I121296143"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Weixin Nie","raw_affiliation_strings":["School of Physics and Electronic Science, Hunan University of Science and Technology, China"],"affiliations":[{"raw_affiliation_string":"School of Physics and Electronic Science, Hunan University of Science and Technology, China","institution_ids":["https://openalex.org/I121296143"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5103164852","display_name":"Qiangguo Yu","orcid":"https://orcid.org/0000-0003-4280-7382"},"institutions":[{"id":"https://openalex.org/I3018263800","display_name":"Huzhou University","ror":"https://ror.org/04mvpxy20","country_code":"CN","type":"education","lineage":["https://openalex.org/I3018263800"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Qiangguo Yu","raw_affiliation_strings":["School of Electronic Information, Huzhou College, China"],"affiliations":[{"raw_affiliation_string":"School of Electronic Information, Huzhou College, China","institution_ids":["https://openalex.org/I3018263800"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5021133124","display_name":"Guozheng Nie","orcid":"https://orcid.org/0000-0002-4303-0686"},"institutions":[{"id":"https://openalex.org/I121296143","display_name":"Hunan University of Science and Technology","ror":"https://ror.org/02m9vrb24","country_code":"CN","type":"education","lineage":["https://openalex.org/I121296143"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Guozheng Nie","raw_affiliation_strings":["School of Physics and Electronic Science, Hunan University of Science and Technology, China"],"affiliations":[{"raw_affiliation_string":"School of Physics and Electronic Science, Hunan University of Science and Technology, China","institution_ids":["https://openalex.org/I121296143"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5054878542"],"corresponding_institution_ids":["https://openalex.org/I121296143"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.21313507,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1053","last_page":"1058"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T12941","display_name":"Embedded Systems and FPGA Design","score":0.6345000267028809,"subfield":{"id":"https://openalex.org/subfields/2207","display_name":"Control and Systems Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T12941","display_name":"Embedded Systems and FPGA Design","score":0.6345000267028809,"subfield":{"id":"https://openalex.org/subfields/2207","display_name":"Control and Systems Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T13344","display_name":"Industrial Automation and Control Systems","score":0.6258999705314636,"subfield":{"id":"https://openalex.org/subfields/2207","display_name":"Control and Systems Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12810","display_name":"Real-time simulation and control systems","score":0.5935999751091003,"subfield":{"id":"https://openalex.org/subfields/2207","display_name":"Control and Systems Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.8356156349182129},{"id":"https://openalex.org/keywords/fifo","display_name":"FIFO (computing and electronics)","score":0.7859723567962646},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.7250432968139648},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.679344892501831},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.665286123752594},{"id":"https://openalex.org/keywords/controller","display_name":"Controller (irrigation)","score":0.6033878922462463},{"id":"https://openalex.org/keywords/terminal","display_name":"Terminal (telecommunication)","score":0.5289514064788818},{"id":"https://openalex.org/keywords/memory-controller","display_name":"Memory controller","score":0.413947194814682},{"id":"https://openalex.org/keywords/scheme","display_name":"Scheme (mathematics)","score":0.413699209690094},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.22869068384170532}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.8356156349182129},{"id":"https://openalex.org/C2777145635","wikidata":"https://www.wikidata.org/wiki/Q515636","display_name":"FIFO (computing and electronics)","level":2,"score":0.7859723567962646},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.7250432968139648},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.679344892501831},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.665286123752594},{"id":"https://openalex.org/C203479927","wikidata":"https://www.wikidata.org/wiki/Q5165939","display_name":"Controller (irrigation)","level":2,"score":0.6033878922462463},{"id":"https://openalex.org/C2779664074","wikidata":"https://www.wikidata.org/wiki/Q3518405","display_name":"Terminal (telecommunication)","level":2,"score":0.5289514064788818},{"id":"https://openalex.org/C100800780","wikidata":"https://www.wikidata.org/wiki/Q1175867","display_name":"Memory controller","level":3,"score":0.413947194814682},{"id":"https://openalex.org/C77618280","wikidata":"https://www.wikidata.org/wiki/Q1155772","display_name":"Scheme (mathematics)","level":2,"score":0.413699209690094},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.22869068384170532},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C6557445","wikidata":"https://www.wikidata.org/wiki/Q173113","display_name":"Agronomy","level":1,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C134306372","wikidata":"https://www.wikidata.org/wiki/Q7754","display_name":"Mathematical analysis","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/3584376.3584564","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3584376.3584564","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2022 4th International Conference on Robotics, Intelligent Control and Artificial Intelligence","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":11,"referenced_works":["https://openalex.org/W988771730","https://openalex.org/W1967098186","https://openalex.org/W2013765583","https://openalex.org/W2328862110","https://openalex.org/W2555861474","https://openalex.org/W2883426667","https://openalex.org/W2896751292","https://openalex.org/W3165071142","https://openalex.org/W3209615710","https://openalex.org/W4220845802","https://openalex.org/W4229065126"],"related_works":["https://openalex.org/W3211557223","https://openalex.org/W2007036916","https://openalex.org/W2120266540","https://openalex.org/W872563264","https://openalex.org/W2350621393","https://openalex.org/W2038831013","https://openalex.org/W2362082090","https://openalex.org/W2558008088","https://openalex.org/W2893763626","https://openalex.org/W2317222294"],"abstract_inverted_index":{"Portable":[0],"data":[1,25,67,121],"monitor":[2,135],"is":[3,8,53],"a":[4,44,105,151,179,183],"special":[5],"terminal":[6,19,52,64,174],"that":[7,131,171],"widely":[9],"used":[10],"in":[11,43,79,165,182],"construction":[12],"machinery":[13],"to":[14],"assist":[15],"the":[16,22,27,31,38,50,69,82,87,132,147,159,162,166,172],"driver.":[17,83],"The":[18,62,84,101,126],"can":[20,40,155,175],"sense":[21],"running":[23,163],"real-time":[24],"of":[26,81,90,134],"machine,":[28],"such":[29],"as":[30],"fuel":[32],"volume":[33],"and":[34,75,86,120,142,146],"engine":[35,73],"speed,":[36],"so":[37],"machine":[39],"be":[41],"driven":[42],"standardized":[45],"manner.":[46],"In":[47],"this":[48],"paper,":[49],"portable":[51],"designed":[54,63,173],"based":[55,98],"on":[56,68,97,99],"Field":[57],"Programmable":[58],"Gate":[59],"Array":[60],"(FPGA).":[61],"mainly":[65],"collects":[66],"equipment":[70],"operation":[71],"status,":[72],"parameters,":[74],"blind":[76],"area":[77],"images":[78],"front":[80],"scheme":[85,149],"implementation":[88,133],"details":[89],"each":[91],"functional":[92],"module":[93],"are":[94],"also":[95],"focused":[96],"FPGA.":[100],"key":[102],"features":[103],"include":[104],"16-bit":[106],"SDRAM":[107],"controller,":[108],"serial":[109],"flash":[110],"controller":[111,117],"with":[112,118,123,150],"100MHz":[113,152],"clock,":[114],"industrial":[115],"LCD":[116],"FIFO":[119],"acquisition":[122],"dual-port":[124],"RAM.":[125],"FPGA":[127],"synthesis":[128],"results":[129,164],"show":[130],"uses":[136],"5871":[137],"Look":[138],"Up":[139],"Tables":[140],"(LUTs)":[141],"245888":[143],"memory":[144],"bits,":[145],"design":[148],"system":[153],"clock":[154],"work":[156],"stably.":[157],"At":[158],"same":[160],"time,":[161],"practical":[167],"engineering":[168],"application":[169],"indicate":[170],"run":[176],"reliably":[177],"for":[178],"long":[180],"time":[181],"harsh":[184],"working":[185],"environment.":[186]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}