{"id":"https://openalex.org/W4378800998","doi":"https://doi.org/10.1145/3583781.3590304","title":"RAGA: Resource-Aware Tree-Splitting for High Performance Knuth-Yao-based Discrete Gaussian Sampling on FPGAs","display_name":"RAGA: Resource-Aware Tree-Splitting for High Performance Knuth-Yao-based Discrete Gaussian Sampling on FPGAs","publication_year":2023,"publication_date":"2023-05-31","ids":{"openalex":"https://openalex.org/W4378800998","doi":"https://doi.org/10.1145/3583781.3590304"},"language":"en","primary_location":{"id":"doi:10.1145/3583781.3590304","is_oa":true,"landing_page_url":"https://doi.org/10.1145/3583781.3590304","pdf_url":"https://dl.acm.org/doi/pdf/10.1145/3583781.3590304","source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the Great Lakes Symposium on VLSI 2023","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"gold","oa_url":"https://dl.acm.org/doi/pdf/10.1145/3583781.3590304","any_repository_has_fulltext":null},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5092052204","display_name":"Zachary J. Ellis","orcid":"https://orcid.org/0009-0004-6381-6362"},"institutions":[{"id":"https://openalex.org/I130701444","display_name":"Georgia Institute of Technology","ror":"https://ror.org/01zkghx44","country_code":"US","type":"education","lineage":["https://openalex.org/I130701444"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Zachary J. Ellis","raw_affiliation_strings":["Georgia Institute of Technology, Atlanta, GA, USA"],"affiliations":[{"raw_affiliation_string":"Georgia Institute of Technology, Atlanta, GA, USA","institution_ids":["https://openalex.org/I130701444"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5085048381","display_name":"Anupam Golder","orcid":"https://orcid.org/0000-0003-0725-1593"},"institutions":[{"id":"https://openalex.org/I130701444","display_name":"Georgia Institute of Technology","ror":"https://ror.org/01zkghx44","country_code":"US","type":"education","lineage":["https://openalex.org/I130701444"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Anupam Golder","raw_affiliation_strings":["Georgia Institute of Technology, Atlanta, GA, USA"],"affiliations":[{"raw_affiliation_string":"Georgia Institute of Technology, Atlanta, GA, USA","institution_ids":["https://openalex.org/I130701444"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5068941759","display_name":"Addison J. Elliott","orcid":"https://orcid.org/0009-0008-9031-0614"},"institutions":[{"id":"https://openalex.org/I130701444","display_name":"Georgia Institute of Technology","ror":"https://ror.org/01zkghx44","country_code":"US","type":"education","lineage":["https://openalex.org/I130701444"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Addison J. Elliott","raw_affiliation_strings":["Georgia Institute of Technology, Atlanta, GA, USA"],"affiliations":[{"raw_affiliation_string":"Georgia Institute of Technology, Atlanta, GA, USA","institution_ids":["https://openalex.org/I130701444"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5091408102","display_name":"Arijit Raychowdhury","orcid":"https://orcid.org/0000-0001-8391-0576"},"institutions":[{"id":"https://openalex.org/I130701444","display_name":"Georgia Institute of Technology","ror":"https://ror.org/01zkghx44","country_code":"US","type":"education","lineage":["https://openalex.org/I130701444"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Arijit Raychowdhury","raw_affiliation_strings":["Georgia Institute of Technology, Atlanta, GA, USA"],"affiliations":[{"raw_affiliation_string":"Georgia Institute of Technology, Atlanta, GA, USA","institution_ids":["https://openalex.org/I130701444"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5092052204"],"corresponding_institution_ids":["https://openalex.org/I130701444"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":true,"cited_by_count":0,"citation_normalized_percentile":{"value":0.05297967,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"443","last_page":"447"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10237","display_name":"Cryptography and Data Security","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10237","display_name":"Cryptography and Data Security","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11130","display_name":"Coding theory and cryptography","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10951","display_name":"Cryptographic Implementations and Security","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7475504279136658},{"id":"https://openalex.org/keywords/lookup-table","display_name":"Lookup table","score":0.7123517990112305},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6953737735748291},{"id":"https://openalex.org/keywords/virtex","display_name":"Virtex","score":0.6519244313240051},{"id":"https://openalex.org/keywords/datapath","display_name":"Datapath","score":0.6197248101234436},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5919934511184692},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.4251716434955597},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.27538925409317017}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7475504279136658},{"id":"https://openalex.org/C134835016","wikidata":"https://www.wikidata.org/wiki/Q690265","display_name":"Lookup table","level":2,"score":0.7123517990112305},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6953737735748291},{"id":"https://openalex.org/C2777674469","wikidata":"https://www.wikidata.org/wiki/Q20741011","display_name":"Virtex","level":3,"score":0.6519244313240051},{"id":"https://openalex.org/C2781198647","wikidata":"https://www.wikidata.org/wiki/Q1633673","display_name":"Datapath","level":2,"score":0.6197248101234436},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5919934511184692},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.4251716434955597},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.27538925409317017},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/3583781.3590304","is_oa":true,"landing_page_url":"https://doi.org/10.1145/3583781.3590304","pdf_url":"https://dl.acm.org/doi/pdf/10.1145/3583781.3590304","source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the Great Lakes Symposium on VLSI 2023","raw_type":"proceedings-article"}],"best_oa_location":{"id":"doi:10.1145/3583781.3590304","is_oa":true,"landing_page_url":"https://doi.org/10.1145/3583781.3590304","pdf_url":"https://dl.acm.org/doi/pdf/10.1145/3583781.3590304","source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the Great Lakes Symposium on VLSI 2023","raw_type":"proceedings-article"},"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/8","display_name":"Decent work and economic growth","score":0.4399999976158142}],"awards":[{"id":"https://openalex.org/G5429611752","display_name":null,"funder_award_id":"1935534 and 171746","funder_id":"https://openalex.org/F4320306076","funder_display_name":"National Science Foundation"},{"id":"https://openalex.org/G6307504972","display_name":"SaTC: CORE: Small: Collaborative: EM and Power Side-Channel Attack Immunity through High-Efficiency Hardware Obfuscations","funder_award_id":"1717467","funder_id":"https://openalex.org/F4320306076","funder_display_name":"National Science Foundation"},{"id":"https://openalex.org/G796966618","display_name":null,"funder_award_id":"1935534","funder_id":"https://openalex.org/F4320306076","funder_display_name":"National Science Foundation"},{"id":"https://openalex.org/G848032724","display_name":null,"funder_award_id":"Science","funder_id":"https://openalex.org/F4320306076","funder_display_name":"National Science Foundation"},{"id":"https://openalex.org/G8661706960","display_name":null,"funder_award_id":"3059.001","funder_id":"https://openalex.org/F4320306087","funder_display_name":"Semiconductor Research Corporation"}],"funders":[{"id":"https://openalex.org/F4320306076","display_name":"National Science Foundation","ror":"https://ror.org/021nxhr62"},{"id":"https://openalex.org/F4320306087","display_name":"Semiconductor Research Corporation","ror":"https://ror.org/047z4n946"}],"has_content":{"pdf":true,"grobid_xml":true},"content_urls":{"pdf":"https://content.openalex.org/works/W4378800998.pdf","grobid_xml":"https://content.openalex.org/works/W4378800998.grobid-xml"},"referenced_works_count":7,"referenced_works":["https://openalex.org/W1603934303","https://openalex.org/W2106970188","https://openalex.org/W2563052397","https://openalex.org/W2792220042","https://openalex.org/W3012228761","https://openalex.org/W3035749312","https://openalex.org/W3198814793"],"related_works":["https://openalex.org/W2134024094","https://openalex.org/W4235839877","https://openalex.org/W2544043553","https://openalex.org/W2546284597","https://openalex.org/W2348562861","https://openalex.org/W2117300767","https://openalex.org/W2024574431","https://openalex.org/W2540393334","https://openalex.org/W1983570530","https://openalex.org/W2062932566"],"abstract_inverted_index":{"In":[0],"this":[1],"work,":[2],"we":[3],"present":[4],"a":[5,57,65],"high-performance":[6],"architecture":[7,31],"for":[8,23,52,81,120],"Discrete":[9],"Gaussian":[10],"(DG)":[11],"sampling":[12,55,83],"used":[13],"in":[14,67,116],"lattice-based":[15],"cryptography":[16],"(LBC)":[17],"through":[18],"lookup":[19],"table":[20],"(LUT)":[21],"optimization":[22],"the":[24,46,68,74,104,112],"combinational":[25],"datapath":[26],"as":[27,29],"well":[28],"FPGA":[30],"aware":[32],"pipelining":[33],"to":[34,73,110],"reduce":[35],"resource":[36],"utilization":[37],"and":[38],"decrease":[39],"latency.":[40],"The":[41,101],"proposed":[42],"tree-splitting":[43],"technique":[44,106],"translates":[45],"discrete":[47],"distribution":[48],"generating":[49],"(DDG)":[50],"tree":[51],"Knuth-Yao-based":[53],"non-uniform":[54],"into":[56],"LUT-based":[58],"logic":[59],"with":[60,84],"pipelined":[61],"architecture.":[62],"This":[63],"allows":[64,108],"reduction":[66],"area-time":[69],"product":[70],"(ATP)":[71],"compared":[72],"most":[75],"efficient":[76],"current":[77],"state-of-the-art":[78],"(SotA)":[79],"designs":[80],"DG":[82,122],"standard":[85],"deviation,":[86],"(\u03c3":[87],"=":[88],"3.19/6.15543/8.5)":[89],"by":[90],"96%/14%/56%":[91],"on":[92],"Virtex-7/Virtex-6/Artix-7":[93],"FPGAs,":[94],"while":[95],"running":[96],"at":[97],"709/580/440":[98],"MHz,":[99],"respectively.":[100],"simplicity":[102],"of":[103],"translation":[105],"also":[107],"us":[109],"automate":[111],"design":[113],"flow,":[114],"resulting":[115],"quick":[117],"design-space":[118],"exploration":[119],"different":[121],"distributions.":[123]},"counts_by_year":[],"updated_date":"2026-03-18T14:38:29.013473","created_date":"2025-10-10T00:00:00"}
