{"id":"https://openalex.org/W4378800754","doi":"https://doi.org/10.1145/3583781.3590231","title":"SPARK: A Scalable Partitioning and Routing Framework for Multi-FPGA Systems","display_name":"SPARK: A Scalable Partitioning and Routing Framework for Multi-FPGA Systems","publication_year":2023,"publication_date":"2023-05-31","ids":{"openalex":"https://openalex.org/W4378800754","doi":"https://doi.org/10.1145/3583781.3590231"},"language":"en","primary_location":{"id":"doi:10.1145/3583781.3590231","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3583781.3590231","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the Great Lakes Symposium on VLSI 2023","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5037988878","display_name":"Xinshi Zang","orcid":"https://orcid.org/0009-0002-7889-4481"},"institutions":[{"id":"https://openalex.org/I177725633","display_name":"Chinese University of Hong Kong","ror":"https://ror.org/00t33hh48","country_code":"CN","type":"education","lineage":["https://openalex.org/I177725633"]}],"countries":["CN"],"is_corresponding":true,"raw_author_name":"Xinshi Zang","raw_affiliation_strings":["The Chinese University of Hong Kong, Hong Kong, Hong Kong"],"affiliations":[{"raw_affiliation_string":"The Chinese University of Hong Kong, Hong Kong, Hong Kong","institution_ids":["https://openalex.org/I177725633"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5070795253","display_name":"Evangeline F. Y. Young","orcid":"https://orcid.org/0000-0003-0623-1590"},"institutions":[{"id":"https://openalex.org/I177725633","display_name":"Chinese University of Hong Kong","ror":"https://ror.org/00t33hh48","country_code":"CN","type":"education","lineage":["https://openalex.org/I177725633"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Evangeline F.Y. Young","raw_affiliation_strings":["The Chinese University of Hong Kong, Hong Kong, Hong Kong"],"affiliations":[{"raw_affiliation_string":"The Chinese University of Hong Kong, Hong Kong, Hong Kong","institution_ids":["https://openalex.org/I177725633"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5053378706","display_name":"Martin D. F. Wong","orcid":"https://orcid.org/0000-0001-8274-9688"},"institutions":[{"id":"https://openalex.org/I177725633","display_name":"Chinese University of Hong Kong","ror":"https://ror.org/00t33hh48","country_code":"CN","type":"education","lineage":["https://openalex.org/I177725633"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Martin D.F. Wong","raw_affiliation_strings":["The Chinese University of Hong Kong, Hong Kong, Hong Kong"],"affiliations":[{"raw_affiliation_string":"The Chinese University of Hong Kong, Hong Kong, Hong Kong","institution_ids":["https://openalex.org/I177725633"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5037988878"],"corresponding_institution_ids":["https://openalex.org/I177725633"],"apc_list":null,"apc_paid":null,"fwci":0.6686,"has_fulltext":false,"cited_by_count":5,"citation_normalized_percentile":{"value":0.67824621,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"593","last_page":"598"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9987000226974487,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.8254457712173462},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7486954927444458},{"id":"https://openalex.org/keywords/scalability","display_name":"Scalability","score":0.704982340335846},{"id":"https://openalex.org/keywords/spark","display_name":"SPARK (programming language)","score":0.5750612020492554},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.5412736535072327},{"id":"https://openalex.org/keywords/fpga-prototype","display_name":"FPGA prototype","score":0.5208104848861694},{"id":"https://openalex.org/keywords/emulation","display_name":"Emulation","score":0.5072019100189209},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4485071897506714},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.41577911376953125},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3865508437156677}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.8254457712173462},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7486954927444458},{"id":"https://openalex.org/C48044578","wikidata":"https://www.wikidata.org/wiki/Q727490","display_name":"Scalability","level":2,"score":0.704982340335846},{"id":"https://openalex.org/C2781215313","wikidata":"https://www.wikidata.org/wiki/Q3493345","display_name":"SPARK (programming language)","level":2,"score":0.5750612020492554},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.5412736535072327},{"id":"https://openalex.org/C203864433","wikidata":"https://www.wikidata.org/wiki/Q5426992","display_name":"FPGA prototype","level":3,"score":0.5208104848861694},{"id":"https://openalex.org/C149810388","wikidata":"https://www.wikidata.org/wiki/Q5374873","display_name":"Emulation","level":2,"score":0.5072019100189209},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4485071897506714},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.41577911376953125},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3865508437156677},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0},{"id":"https://openalex.org/C77088390","wikidata":"https://www.wikidata.org/wiki/Q8513","display_name":"Database","level":1,"score":0.0},{"id":"https://openalex.org/C50522688","wikidata":"https://www.wikidata.org/wiki/Q189833","display_name":"Economic growth","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/3583781.3590231","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3583781.3590231","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the Great Lakes Symposium on VLSI 2023","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","score":0.5799999833106995,"id":"https://metadata.un.org/sdg/9"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":12,"referenced_works":["https://openalex.org/W32337268","https://openalex.org/W288065879","https://openalex.org/W2003193909","https://openalex.org/W2101037299","https://openalex.org/W2164340799","https://openalex.org/W2914161519","https://openalex.org/W2963489471","https://openalex.org/W3011427649","https://openalex.org/W3043859075","https://openalex.org/W3213962700","https://openalex.org/W4200036442","https://openalex.org/W4242608849"],"related_works":["https://openalex.org/W2998132311","https://openalex.org/W2110265185","https://openalex.org/W3146360095","https://openalex.org/W2207067480","https://openalex.org/W4383823603","https://openalex.org/W2332075903","https://openalex.org/W1579891439","https://openalex.org/W2291257309","https://openalex.org/W2082487009","https://openalex.org/W272033699"],"abstract_inverted_index":{"With":[0],"the":[1,35,85,92,103,136,146,152,165,168],"size":[2,9,119],"of":[3,12,29,88,172],"modern":[4],"VLSI":[5],"circuits":[6],"growing":[7],"in":[8,20,54,140],"to":[10,116,134],"billions":[11],"transistors,":[13],"multi-FPGA":[14,41,76,141],"systems":[15,142],"have":[16],"been":[17],"widely":[18],"applied":[19],"circuit":[21,155],"emulation":[22],"and":[23,33,57,66,69,84,130,138,144,159,170],"prototyping.":[24],"To":[25,90],"make":[26],"full":[27],"advantage":[28],"limited":[30],"FPGA":[31,158,162],"resources":[32,98],"improve":[34,145],"system":[36,42,77,147],"frequency,":[37],"designing":[38],"a":[39,44,64,75],"flexible":[40],"with":[43,78,111],"corresponding":[45],"design":[46],"compilation":[47],"flow":[48],"is":[49],"an":[50,79,112],"important":[51],"research":[52],"problem":[53],"both":[55],"industry":[56,166],"academia.":[58],"In":[59],"this":[60],"work,":[61],"we":[62],"propose":[63,125],"practical":[65],"scalable":[67],"partitioning":[68,106],"routing":[70,129],"framework,":[71],"named":[72],"SPARK,":[73],"for":[74,99,157],"adjustable":[80],"near-square":[81],"mesh":[82],"shape":[83],"minimum":[86],"number":[87],"FPGAs.":[89],"resolve":[91],"significant":[93],"constraints":[94],"on":[95],"multiple":[96],"hardware":[97],"partitioning,":[100],"SPARK":[101],"leverages":[102],"general":[104],"hypergraph":[105],"tool":[107],"by":[108],"combining":[109],"it":[110],"efficient":[113],"legalization":[114],"algorithm":[115],"minimize":[117],"cut":[118],"without":[120],"resource":[121],"overflow.":[122],"We":[123],"also":[124],"novel":[126],"max_cut-driven":[127],"maze":[128],"max_hop-driven":[131],"refinement":[132],"algorithms":[133],"optimize":[135],"max_cut":[137],"max_hop":[139],"meanwhile":[143],"frequency.":[148],"Extensive":[149],"experiments":[150],"using":[151],"largest":[153],"public":[154],"benchmarks":[156],"several":[160],"small":[161],"settings":[163],"from":[164],"demonstrate":[167],"effectiveness":[169],"efficiency":[171],"SPARK.":[173]},"counts_by_year":[{"year":2025,"cited_by_count":2},{"year":2024,"cited_by_count":2},{"year":2023,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}