{"id":"https://openalex.org/W4226372463","doi":"https://doi.org/10.1145/3578360.3580273","title":"RL4ReAl: Reinforcement Learning for Register Allocation","display_name":"RL4ReAl: Reinforcement Learning for Register Allocation","publication_year":2023,"publication_date":"2023-02-17","ids":{"openalex":"https://openalex.org/W4226372463","doi":"https://doi.org/10.1145/3578360.3580273"},"language":"en","primary_location":{"id":"doi:10.1145/3578360.3580273","is_oa":true,"landing_page_url":"https://doi.org/10.1145/3578360.3580273","pdf_url":null,"source":null,"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 32nd ACM SIGPLAN International Conference on Compiler Construction","raw_type":"proceedings-article"},"type":"preprint","indexed_in":["arxiv","crossref"],"open_access":{"is_oa":true,"oa_status":"gold","oa_url":"https://doi.org/10.1145/3578360.3580273","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5011873416","display_name":"S. VenkataKeerthy","orcid":"https://orcid.org/0000-0003-1393-7321"},"institutions":[{"id":"https://openalex.org/I65181880","display_name":"Indian Institute of Technology Hyderabad","ror":"https://ror.org/01j4v3x97","country_code":"IN","type":"education","lineage":["https://openalex.org/I65181880"]}],"countries":["IN"],"is_corresponding":true,"raw_author_name":"S. VenkataKeerthy","raw_affiliation_strings":["IIT Hyderabad, Hyderabad, India"],"affiliations":[{"raw_affiliation_string":"IIT Hyderabad, Hyderabad, India","institution_ids":["https://openalex.org/I65181880"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5057161196","display_name":"Siddharth Jain","orcid":"https://orcid.org/0000-0003-3801-7759"},"institutions":[{"id":"https://openalex.org/I65181880","display_name":"Indian Institute of Technology Hyderabad","ror":"https://ror.org/01j4v3x97","country_code":"IN","type":"education","lineage":["https://openalex.org/I65181880"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Siddharth Jain","raw_affiliation_strings":["IIT Hyderabad, Hyderabad, India"],"affiliations":[{"raw_affiliation_string":"IIT Hyderabad, Hyderabad, India","institution_ids":["https://openalex.org/I65181880"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5113988700","display_name":"Anilava Kundu","orcid":null},"institutions":[{"id":"https://openalex.org/I65181880","display_name":"Indian Institute of Technology Hyderabad","ror":"https://ror.org/01j4v3x97","country_code":"IN","type":"education","lineage":["https://openalex.org/I65181880"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Anilava Kundu","raw_affiliation_strings":["IIT Hyderabad, Hyderabad, India"],"affiliations":[{"raw_affiliation_string":"IIT Hyderabad, Hyderabad, India","institution_ids":["https://openalex.org/I65181880"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5060546521","display_name":"Rohit Aggarwal","orcid":"https://orcid.org/0009-0007-1047-2000"},"institutions":[{"id":"https://openalex.org/I65181880","display_name":"Indian Institute of Technology Hyderabad","ror":"https://ror.org/01j4v3x97","country_code":"IN","type":"education","lineage":["https://openalex.org/I65181880"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Rohit Aggarwal","raw_affiliation_strings":["IIT Hyderabad, Hyderabad, India"],"affiliations":[{"raw_affiliation_string":"IIT Hyderabad, Hyderabad, India","institution_ids":["https://openalex.org/I65181880"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5063162788","display_name":"Albert Cohen","orcid":"https://orcid.org/0000-0002-8866-5343"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Albert Cohen","raw_affiliation_strings":["Google, France"],"affiliations":[{"raw_affiliation_string":"Google, France","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5075524478","display_name":"Ramakrishna Upadrasta","orcid":"https://orcid.org/0000-0002-5290-3266"},"institutions":[{"id":"https://openalex.org/I65181880","display_name":"Indian Institute of Technology Hyderabad","ror":"https://ror.org/01j4v3x97","country_code":"IN","type":"education","lineage":["https://openalex.org/I65181880"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Ramakrishna Upadrasta","raw_affiliation_strings":["IIT Hyderabad, Hyderabad, India"],"affiliations":[{"raw_affiliation_string":"IIT Hyderabad, Hyderabad, India","institution_ids":["https://openalex.org/I65181880"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":6,"corresponding_author_ids":["https://openalex.org/A5011873416"],"corresponding_institution_ids":["https://openalex.org/I65181880"],"apc_list":null,"apc_paid":null,"fwci":2.4014,"has_fulltext":false,"cited_by_count":9,"citation_normalized_percentile":{"value":0.87492383,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":98},"biblio":{"volume":null,"issue":null,"first_page":"133","last_page":"144"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9968000054359436,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9968000054359436,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10462","display_name":"Reinforcement Learning in Robotics","score":0.9958999752998352,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11975","display_name":"Evolutionary Algorithms and Applications","score":0.9843000173568726,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.9020927548408508},{"id":"https://openalex.org/keywords/register-allocation","display_name":"Register allocation","score":0.8091145753860474},{"id":"https://openalex.org/keywords/reinforcement-learning","display_name":"Reinforcement learning","score":0.7411699295043945},{"id":"https://openalex.org/keywords/x86","display_name":"x86","score":0.667095959186554},{"id":"https://openalex.org/keywords/allocator","display_name":"Allocator","score":0.6002098321914673},{"id":"https://openalex.org/keywords/modular-design","display_name":"Modular design","score":0.5616651773452759},{"id":"https://openalex.org/keywords/correctness","display_name":"Correctness","score":0.5241304039955139},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.5183047652244568},{"id":"https://openalex.org/keywords/compiler","display_name":"Compiler","score":0.5024855136871338},{"id":"https://openalex.org/keywords/processor-register","display_name":"Processor register","score":0.492364764213562},{"id":"https://openalex.org/keywords/debugging","display_name":"Debugging","score":0.4862755537033081},{"id":"https://openalex.org/keywords/instruction-set","display_name":"Instruction set","score":0.4661864936351776},{"id":"https://openalex.org/keywords/embedding","display_name":"Embedding","score":0.45821163058280945},{"id":"https://openalex.org/keywords/java","display_name":"Java","score":0.4532727301120758},{"id":"https://openalex.org/keywords/set","display_name":"Set (abstract data type)","score":0.44227421283721924},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.43584948778152466},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.4343750774860382},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.4339674115180969},{"id":"https://openalex.org/keywords/executable","display_name":"Executable","score":0.4265245199203491},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.375762403011322},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.2788279056549072},{"id":"https://openalex.org/keywords/memory-address","display_name":"Memory address","score":0.11678719520568848}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.9020927548408508},{"id":"https://openalex.org/C128916667","wikidata":"https://www.wikidata.org/wiki/Q1343660","display_name":"Register allocation","level":3,"score":0.8091145753860474},{"id":"https://openalex.org/C97541855","wikidata":"https://www.wikidata.org/wiki/Q830687","display_name":"Reinforcement learning","level":2,"score":0.7411699295043945},{"id":"https://openalex.org/C170723468","wikidata":"https://www.wikidata.org/wiki/Q182933","display_name":"x86","level":3,"score":0.667095959186554},{"id":"https://openalex.org/C162262903","wikidata":"https://www.wikidata.org/wiki/Q343527","display_name":"Allocator","level":2,"score":0.6002098321914673},{"id":"https://openalex.org/C101468663","wikidata":"https://www.wikidata.org/wiki/Q1620158","display_name":"Modular design","level":2,"score":0.5616651773452759},{"id":"https://openalex.org/C55439883","wikidata":"https://www.wikidata.org/wiki/Q360812","display_name":"Correctness","level":2,"score":0.5241304039955139},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.5183047652244568},{"id":"https://openalex.org/C169590947","wikidata":"https://www.wikidata.org/wiki/Q47506","display_name":"Compiler","level":2,"score":0.5024855136871338},{"id":"https://openalex.org/C2871975","wikidata":"https://www.wikidata.org/wiki/Q187466","display_name":"Processor register","level":4,"score":0.492364764213562},{"id":"https://openalex.org/C168065819","wikidata":"https://www.wikidata.org/wiki/Q845566","display_name":"Debugging","level":2,"score":0.4862755537033081},{"id":"https://openalex.org/C202491316","wikidata":"https://www.wikidata.org/wiki/Q272683","display_name":"Instruction set","level":2,"score":0.4661864936351776},{"id":"https://openalex.org/C41608201","wikidata":"https://www.wikidata.org/wiki/Q980509","display_name":"Embedding","level":2,"score":0.45821163058280945},{"id":"https://openalex.org/C548217200","wikidata":"https://www.wikidata.org/wiki/Q251","display_name":"Java","level":2,"score":0.4532727301120758},{"id":"https://openalex.org/C177264268","wikidata":"https://www.wikidata.org/wiki/Q1514741","display_name":"Set (abstract data type)","level":2,"score":0.44227421283721924},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.43584948778152466},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.4343750774860382},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.4339674115180969},{"id":"https://openalex.org/C160145156","wikidata":"https://www.wikidata.org/wiki/Q778586","display_name":"Executable","level":2,"score":0.4265245199203491},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.375762403011322},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.2788279056549072},{"id":"https://openalex.org/C153247305","wikidata":"https://www.wikidata.org/wiki/Q835713","display_name":"Memory address","level":3,"score":0.11678719520568848},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1145/3578360.3580273","is_oa":true,"landing_page_url":"https://doi.org/10.1145/3578360.3580273","pdf_url":null,"source":null,"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 32nd ACM SIGPLAN International Conference on Compiler Construction","raw_type":"proceedings-article"},{"id":"pmh:oai:arXiv.org:2204.02013","is_oa":true,"landing_page_url":"http://arxiv.org/abs/2204.02013","pdf_url":"https://arxiv.org/pdf/2204.02013","source":{"id":"https://openalex.org/S4306400194","display_name":"arXiv (Cornell University)","issn_l":null,"issn":null,"is_oa":true,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I205783295","host_organization_name":"Cornell University","host_organization_lineage":["https://openalex.org/I205783295"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"text"}],"best_oa_location":{"id":"doi:10.1145/3578360.3580273","is_oa":true,"landing_page_url":"https://doi.org/10.1145/3578360.3580273","pdf_url":null,"source":null,"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 32nd ACM SIGPLAN International Conference on Compiler Construction","raw_type":"proceedings-article"},"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/4","score":0.4300000071525574,"display_name":"Quality Education"}],"awards":[],"funders":[{"id":"https://openalex.org/F4320307757","display_name":"Advanced Micro Devices","ror":"https://ror.org/04kd6c783"},{"id":"https://openalex.org/F4320309327","display_name":"Google","ror":"https://ror.org/00njsd438"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":50,"referenced_works":["https://openalex.org/W1549929312","https://openalex.org/W1599239188","https://openalex.org/W1766250948","https://openalex.org/W1876846146","https://openalex.org/W1883303451","https://openalex.org/W1980310053","https://openalex.org/W1982205631","https://openalex.org/W2003804316","https://openalex.org/W2011039300","https://openalex.org/W2018768276","https://openalex.org/W2023200270","https://openalex.org/W2044636417","https://openalex.org/W2074352684","https://openalex.org/W2127795553","https://openalex.org/W2133128124","https://openalex.org/W2140191557","https://openalex.org/W2156467401","https://openalex.org/W2156560068","https://openalex.org/W2157331557","https://openalex.org/W2167822297","https://openalex.org/W2736601468","https://openalex.org/W2751060233","https://openalex.org/W2751901133","https://openalex.org/W2766447205","https://openalex.org/W2794150393","https://openalex.org/W2810785043","https://openalex.org/W2888297879","https://openalex.org/W2912500072","https://openalex.org/W2919364174","https://openalex.org/W2971234788","https://openalex.org/W3008788679","https://openalex.org/W3086481683","https://openalex.org/W3107793421","https://openalex.org/W3116350821","https://openalex.org/W3116960032","https://openalex.org/W3118280259","https://openalex.org/W3120378074","https://openalex.org/W3120529295","https://openalex.org/W3127561923","https://openalex.org/W3147809485","https://openalex.org/W3168189449","https://openalex.org/W3200950867","https://openalex.org/W4214484431","https://openalex.org/W4220880378","https://openalex.org/W4225907008","https://openalex.org/W4246166885","https://openalex.org/W4283662726","https://openalex.org/W4288091680","https://openalex.org/W4297670746","https://openalex.org/W4304997382"],"related_works":["https://openalex.org/W4252189340","https://openalex.org/W2104533913","https://openalex.org/W2078229301","https://openalex.org/W2479182427","https://openalex.org/W2755854447","https://openalex.org/W1607259217","https://openalex.org/W2155935413","https://openalex.org/W2084277969","https://openalex.org/W4233450076","https://openalex.org/W2155316957"],"abstract_inverted_index":{"We":[0,15,37,60],"aim":[1],"to":[2],"automate":[3],"decades":[4],"of":[5,33,104],"research":[6],"and":[7,70,76,90],"experience":[8],"in":[9],"register":[10,102],"allocation,":[11],"leveraging":[12],"machine":[13],"learning.":[14],"tackle":[16],"this":[17],"problem":[18,45],"by":[19],"embedding":[20],"a":[21,47,63,68],"multi-agent":[22],"reinforcement":[23],"learning":[24],"algorithm":[25],"within":[26],"LLVM,":[27],"training":[28,75],"it":[29],"with":[30],"the":[31,34,39,44,54,98],"state":[32],"art":[35],"techniques.":[36],"formalize":[38],"constraints":[40],"that":[41,53],"precisely":[42],"define":[43],"for":[46,74],"given":[48],"instruction-set":[49],"architecture,":[50],"while":[51],"ensuring":[52],"generated":[55],"code":[56],"preserves":[57],"semantic":[58],"correctness.":[59],"also":[61],"develop":[62],"gRPC":[64],"based":[65],"framework":[66],"providing":[67],"modular":[69],"efficient":[71],"compiler":[72],"interface":[73],"inference.":[77],"Our":[78,93],"approach":[79],"is":[80],"architecture":[81],"independent:":[82],"we":[83],"show":[84],"experimental":[85],"results":[86,94],"targeting":[87],"Intel":[88],"x86":[89],"ARM":[91],"AArch64.":[92],"match":[95],"or":[96],"out-perform":[97],"heavily":[99],"tuned,":[100],"production-grade":[101],"allocators":[103],"LLVM.":[105]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2025,"cited_by_count":3},{"year":2024,"cited_by_count":3},{"year":2023,"cited_by_count":1},{"year":2022,"cited_by_count":1}],"updated_date":"2026-04-21T08:09:41.155169","created_date":"2025-10-10T00:00:00"}