{"id":"https://openalex.org/W4318541659","doi":"https://doi.org/10.1145/3575693.3575753","title":"SMAPPIC: Scalable Multi-FPGA Architecture Prototype Platform in the Cloud","display_name":"SMAPPIC: Scalable Multi-FPGA Architecture Prototype Platform in the Cloud","publication_year":2023,"publication_date":"2023-01-27","ids":{"openalex":"https://openalex.org/W4318541659","doi":"https://doi.org/10.1145/3575693.3575753"},"language":"en","primary_location":{"id":"doi:10.1145/3575693.3575753","is_oa":true,"landing_page_url":"https://doi.org/10.1145/3575693.3575753","pdf_url":"https://dl.acm.org/doi/pdf/10.1145/3575693.3575753","source":null,"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 28th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 2","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"gold","oa_url":"https://dl.acm.org/doi/pdf/10.1145/3575693.3575753","any_repository_has_fulltext":null},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5089744025","display_name":"Grigory Chirkov","orcid":"https://orcid.org/0000-0002-9313-3085"},"institutions":[{"id":"https://openalex.org/I20089843","display_name":"Princeton University","ror":"https://ror.org/00hx57361","country_code":"US","type":"education","lineage":["https://openalex.org/I20089843"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Grigory Chirkov","raw_affiliation_strings":["Princeton University, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Princeton University, USA","institution_ids":["https://openalex.org/I20089843"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5080019688","display_name":"David Wentzlaff","orcid":"https://orcid.org/0000-0002-6337-5630"},"institutions":[{"id":"https://openalex.org/I20089843","display_name":"Princeton University","ror":"https://ror.org/00hx57361","country_code":"US","type":"education","lineage":["https://openalex.org/I20089843"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"David Wentzlaff","raw_affiliation_strings":["Princeton University, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Princeton University, USA","institution_ids":["https://openalex.org/I20089843"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I20089843"],"apc_list":null,"apc_paid":null,"fwci":3.1302,"has_fulltext":true,"cited_by_count":11,"citation_normalized_percentile":{"value":0.9150585,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":95,"max":98},"biblio":{"volume":null,"issue":null,"first_page":"733","last_page":"746"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.8689190149307251},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7761202454566956},{"id":"https://openalex.org/keywords/scalability","display_name":"Scalability","score":0.7567716836929321},{"id":"https://openalex.org/keywords/cloud-computing","display_name":"Cloud computing","score":0.6995278596878052},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.633779764175415},{"id":"https://openalex.org/keywords/fpga-prototype","display_name":"FPGA prototype","score":0.5955297946929932},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.5541067123413086},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5437527894973755},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.5320742130279541},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.5241906046867371},{"id":"https://openalex.org/keywords/reconfigurable-computing","display_name":"Reconfigurable computing","score":0.43993932008743286},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.31436291337013245}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.8689190149307251},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7761202454566956},{"id":"https://openalex.org/C48044578","wikidata":"https://www.wikidata.org/wiki/Q727490","display_name":"Scalability","level":2,"score":0.7567716836929321},{"id":"https://openalex.org/C79974875","wikidata":"https://www.wikidata.org/wiki/Q483639","display_name":"Cloud computing","level":2,"score":0.6995278596878052},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.633779764175415},{"id":"https://openalex.org/C203864433","wikidata":"https://www.wikidata.org/wiki/Q5426992","display_name":"FPGA prototype","level":3,"score":0.5955297946929932},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.5541067123413086},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5437527894973755},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.5320742130279541},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.5241906046867371},{"id":"https://openalex.org/C142962650","wikidata":"https://www.wikidata.org/wiki/Q240838","display_name":"Reconfigurable computing","level":3,"score":0.43993932008743286},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.31436291337013245},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/3575693.3575753","is_oa":true,"landing_page_url":"https://doi.org/10.1145/3575693.3575753","pdf_url":"https://dl.acm.org/doi/pdf/10.1145/3575693.3575753","source":null,"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 28th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 2","raw_type":"proceedings-article"}],"best_oa_location":{"id":"doi:10.1145/3575693.3575753","is_oa":true,"landing_page_url":"https://doi.org/10.1145/3575693.3575753","pdf_url":"https://dl.acm.org/doi/pdf/10.1145/3575693.3575753","source":null,"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 28th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 2","raw_type":"proceedings-article"},"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","score":0.6499999761581421,"id":"https://metadata.un.org/sdg/9"}],"awards":[{"id":"https://openalex.org/G1501292335","display_name":null,"funder_award_id":"FA8650-18-2-7852,FA8650-18-2-7862","funder_id":"https://openalex.org/F4320332180","funder_display_name":"Defense Advanced Research Projects Agency"},{"id":"https://openalex.org/G2867504289","display_name":null,"funder_award_id":"No. FA8650-18-2-7852","funder_id":"https://openalex.org/F4320338294","funder_display_name":"Air Force Research Laboratory"},{"id":"https://openalex.org/G352640593","display_name":null,"funder_award_id":"FA8650-18-2-7852","funder_id":"https://openalex.org/F4320332180","funder_display_name":"Defense Advanced Research Projects Agency"},{"id":"https://openalex.org/G4582951547","display_name":null,"funder_award_id":"FA8650-18-2-7862","funder_id":"https://openalex.org/F4320338294","funder_display_name":"Air Force Research Laboratory"},{"id":"https://openalex.org/G5330319752","display_name":null,"funder_award_id":"CNS-1823222","funder_id":"https://openalex.org/F4320306076","funder_display_name":"National Science Foundation"},{"id":"https://openalex.org/G5609375043","display_name":null,"funder_award_id":"FA8650-18-2-7852","funder_id":"https://openalex.org/F4320338294","funder_display_name":"Air Force Research Laboratory"},{"id":"https://openalex.org/G5879311188","display_name":"CRI: CI-New: OpenPiton 2: Enabling Open Source Manycore Hardware Research","funder_award_id":"1823222","funder_id":"https://openalex.org/F4320306076","funder_display_name":"National Science Foundation"},{"id":"https://openalex.org/G6817207131","display_name":null,"funder_award_id":"No. FA8650-18-2-7852","funder_id":"https://openalex.org/F4320332180","funder_display_name":"Defense Advanced Research Projects Agency"},{"id":"https://openalex.org/G7203148941","display_name":null,"funder_award_id":"FA8650-18-2-7862","funder_id":"https://openalex.org/F4320332180","funder_display_name":"Defense Advanced Research Projects Agency"}],"funders":[{"id":"https://openalex.org/F4320306076","display_name":"National Science Foundation","ror":"https://ror.org/021nxhr62"},{"id":"https://openalex.org/F4320332180","display_name":"Defense Advanced Research Projects Agency","ror":"https://ror.org/02caytj08"},{"id":"https://openalex.org/F4320332815","display_name":"Advanced Research Projects Agency","ror":"https://ror.org/02caytj08"},{"id":"https://openalex.org/F4320338294","display_name":"Air Force Research Laboratory","ror":"https://ror.org/02e2egq70"}],"has_content":{"pdf":true,"grobid_xml":false},"content_urls":{"pdf":"https://content.openalex.org/works/W4318541659.pdf"},"referenced_works_count":36,"referenced_works":["https://openalex.org/W307918303","https://openalex.org/W1523401229","https://openalex.org/W1967605297","https://openalex.org/W2026320578","https://openalex.org/W2032699516","https://openalex.org/W2034062945","https://openalex.org/W2077019175","https://openalex.org/W2097774686","https://openalex.org/W2132078224","https://openalex.org/W2134470641","https://openalex.org/W2137385009","https://openalex.org/W2141600480","https://openalex.org/W2154790323","https://openalex.org/W2155764480","https://openalex.org/W2156360978","https://openalex.org/W2239360558","https://openalex.org/W2621011436","https://openalex.org/W2761689304","https://openalex.org/W2781453246","https://openalex.org/W2794667765","https://openalex.org/W2884267664","https://openalex.org/W2933686492","https://openalex.org/W2936567838","https://openalex.org/W2952928793","https://openalex.org/W3010795619","https://openalex.org/W3011537247","https://openalex.org/W3027123178","https://openalex.org/W3032789745","https://openalex.org/W3188178661","https://openalex.org/W4214569703","https://openalex.org/W4236029802","https://openalex.org/W4251534053","https://openalex.org/W4253751283","https://openalex.org/W4255283632","https://openalex.org/W4281782992","https://openalex.org/W4394648225"],"related_works":["https://openalex.org/W2998132311","https://openalex.org/W2207067480","https://openalex.org/W4383823603","https://openalex.org/W2113648965","https://openalex.org/W2155484023","https://openalex.org/W4200391368","https://openalex.org/W2388221044","https://openalex.org/W3117064361","https://openalex.org/W2984236338","https://openalex.org/W2619213283"],"abstract_inverted_index":{"Traditionally,":[0],"architecture":[1],"prototypes":[2,91],"are":[3,18,110],"built":[4],"on":[5,44,76],"top":[6],"of":[7,29,38,92,132],"FPGA":[8,30,55,121],"infrastructure,":[9],"with":[10],"two":[11],"associated":[12],"problems.":[13],"First,":[14],"very":[15],"large":[16],"FPGAs":[17],"prohibitively":[19],"expensive":[20],"for":[21,71],"most":[22],"people":[23],"and":[24,84,102,120],"institutions.":[25],"Second,":[26],"the":[27,66,81,126,130,139],"burden":[28],"development":[31],"adds":[32],"to":[33,88,128],"an":[34],"already":[35],"uneasy":[36],"life":[37],"researchers,":[39],"especially":[40],"those":[41],"who":[42],"focus":[43],"software.":[45],"Large":[46],"designs":[47],"that":[48,109],"do":[49],"not":[50,111],"fit":[51],"into":[52],"a":[53],"single":[54],"exacerbate":[56],"these":[57],"issues":[58],"even":[59],"more.":[60],"This":[61,123],"work":[62,124],"presents":[63],"SMAPPIC":[64,79,104],"\u2014":[65],"first":[67],"open-source":[68],"prototype":[69],"platform":[70],"shared":[72],"memory":[73],"multi-die":[74],"architectures":[75],"cloud":[77],"FPGAs.":[78],"leverages":[80],"OpenPiton/BYOC":[82],"infrastructure":[83],"AWS":[85],"F1":[86],"instances":[87],"make":[89],"FPGA-based":[90],"System-on-Chips,":[93],"processor":[94],"cores,":[95],"accelerators,":[96],"cache":[97],"subsystems,":[98],"etc.,":[99],"cheap,":[100],"scalable,":[101],"straightforward.":[103],"enables":[105],"many":[106],"use":[107],"cases":[108],"possible":[112],"or":[113],"significantly":[114],"more":[115],"complicated":[116],"in":[117,134,138],"existing":[118],"software":[119],"tools.":[122],"has":[125],"potential":[127],"accelerate":[129],"rate":[131],"innovation":[133],"computer":[135],"engineering":[136],"fields":[137],"nearest":[140],"future.":[141]},"counts_by_year":[{"year":2025,"cited_by_count":2},{"year":2024,"cited_by_count":5},{"year":2023,"cited_by_count":4}],"updated_date":"2026-06-26T08:34:08.712188","created_date":"2025-10-10T00:00:00"}