{"id":"https://openalex.org/W4311119096","doi":"https://doi.org/10.1145/3572919","title":"Polling-Based Memory Interface","display_name":"Polling-Based Memory Interface","publication_year":2022,"publication_date":"2022-12-02","ids":{"openalex":"https://openalex.org/W4311119096","doi":"https://doi.org/10.1145/3572919"},"language":"en","primary_location":{"id":"doi:10.1145/3572919","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3572919","pdf_url":null,"source":{"id":"https://openalex.org/S105046310","display_name":"ACM Transactions on Design Automation of Electronic Systems","issn_l":"1084-4309","issn":["1084-4309","1557-7309"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319798","host_organization_name":"Association for Computing Machinery","host_organization_lineage":["https://openalex.org/P4310319798"],"host_organization_lineage_names":["Association for Computing Machinery"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"ACM Transactions on Design Automation of Electronic Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5101826439","display_name":"Trung Thanh Le","orcid":"https://orcid.org/0000-0001-7686-4508"},"institutions":[{"id":"https://openalex.org/I39422238","display_name":"University of Illinois Chicago","ror":"https://ror.org/02mpq6x41","country_code":"US","type":"education","lineage":["https://openalex.org/I39422238"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Trung Le","raw_affiliation_strings":["University of Illinois at Chicago, Chicago, IL"],"raw_orcid":"https://orcid.org/0000-0001-7686-4508","affiliations":[{"raw_affiliation_string":"University of Illinois at Chicago, Chicago, IL","institution_ids":["https://openalex.org/I39422238"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100423015","display_name":"Zhao Zhang","orcid":"https://orcid.org/0000-0002-2526-1712"},"institutions":[{"id":"https://openalex.org/I39422238","display_name":"University of Illinois Chicago","ror":"https://ror.org/02mpq6x41","country_code":"US","type":"education","lineage":["https://openalex.org/I39422238"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Zhao Zhang","raw_affiliation_strings":["University of Illinois at Chicago, Chicago, IL"],"raw_orcid":"https://orcid.org/0000-0002-2526-1712","affiliations":[{"raw_affiliation_string":"University of Illinois at Chicago, Chicago, IL","institution_ids":["https://openalex.org/I39422238"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5101455512","display_name":"Zhichun Zhu","orcid":"https://orcid.org/0000-0002-7928-9024"},"institutions":[{"id":"https://openalex.org/I39422238","display_name":"University of Illinois Chicago","ror":"https://ror.org/02mpq6x41","country_code":"US","type":"education","lineage":["https://openalex.org/I39422238"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Zhichun Zhu","raw_affiliation_strings":["University of Illinois at Chicago, Chicago, IL"],"raw_orcid":"https://orcid.org/0000-0002-7928-9024","affiliations":[{"raw_affiliation_string":"University of Illinois at Chicago, Chicago, IL","institution_ids":["https://openalex.org/I39422238"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.14462366,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"28","issue":"3","first_page":"1","last_page":"23"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8830524682998657},{"id":"https://openalex.org/keywords/memory-controller","display_name":"Memory controller","score":0.796350359916687},{"id":"https://openalex.org/keywords/registered-memory","display_name":"Registered memory","score":0.7740777730941772},{"id":"https://openalex.org/keywords/interleaved-memory","display_name":"Interleaved memory","score":0.6205207705497742},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5821296572685242},{"id":"https://openalex.org/keywords/polling","display_name":"Polling","score":0.5799568891525269},{"id":"https://openalex.org/keywords/uniform-memory-access","display_name":"Uniform memory access","score":0.48094505071640015},{"id":"https://openalex.org/keywords/flat-memory-model","display_name":"Flat memory model","score":0.46087342500686646},{"id":"https://openalex.org/keywords/extended-memory","display_name":"Extended memory","score":0.4408387839794159},{"id":"https://openalex.org/keywords/memory-refresh","display_name":"Memory refresh","score":0.4258176386356354},{"id":"https://openalex.org/keywords/interface","display_name":"Interface (matter)","score":0.4207739233970642},{"id":"https://openalex.org/keywords/scalability","display_name":"Scalability","score":0.4137704372406006},{"id":"https://openalex.org/keywords/memory-map","display_name":"Memory map","score":0.4102116525173187},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.37898147106170654},{"id":"https://openalex.org/keywords/memory-management","display_name":"Memory management","score":0.3621579110622406},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.35992199182510376},{"id":"https://openalex.org/keywords/computer-memory","display_name":"Computer memory","score":0.3266889750957489},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.24606207013130188},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.22456902265548706}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8830524682998657},{"id":"https://openalex.org/C100800780","wikidata":"https://www.wikidata.org/wiki/Q1175867","display_name":"Memory controller","level":3,"score":0.796350359916687},{"id":"https://openalex.org/C93446704","wikidata":"https://www.wikidata.org/wiki/Q449328","display_name":"Registered memory","level":3,"score":0.7740777730941772},{"id":"https://openalex.org/C63511323","wikidata":"https://www.wikidata.org/wiki/Q908936","display_name":"Interleaved memory","level":4,"score":0.6205207705497742},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5821296572685242},{"id":"https://openalex.org/C204854418","wikidata":"https://www.wikidata.org/wiki/Q1362921","display_name":"Polling","level":2,"score":0.5799568891525269},{"id":"https://openalex.org/C51290061","wikidata":"https://www.wikidata.org/wiki/Q1936765","display_name":"Uniform memory access","level":4,"score":0.48094505071640015},{"id":"https://openalex.org/C57863822","wikidata":"https://www.wikidata.org/wiki/Q905488","display_name":"Flat memory model","level":4,"score":0.46087342500686646},{"id":"https://openalex.org/C171675096","wikidata":"https://www.wikidata.org/wiki/Q1143380","display_name":"Extended memory","level":4,"score":0.4408387839794159},{"id":"https://openalex.org/C87907426","wikidata":"https://www.wikidata.org/wiki/Q6815755","display_name":"Memory refresh","level":4,"score":0.4258176386356354},{"id":"https://openalex.org/C113843644","wikidata":"https://www.wikidata.org/wiki/Q901882","display_name":"Interface (matter)","level":4,"score":0.4207739233970642},{"id":"https://openalex.org/C48044578","wikidata":"https://www.wikidata.org/wiki/Q727490","display_name":"Scalability","level":2,"score":0.4137704372406006},{"id":"https://openalex.org/C74426580","wikidata":"https://www.wikidata.org/wiki/Q719484","display_name":"Memory map","level":3,"score":0.4102116525173187},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.37898147106170654},{"id":"https://openalex.org/C176649486","wikidata":"https://www.wikidata.org/wiki/Q2308807","display_name":"Memory management","level":3,"score":0.3621579110622406},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.35992199182510376},{"id":"https://openalex.org/C92855701","wikidata":"https://www.wikidata.org/wiki/Q5830907","display_name":"Computer memory","level":3,"score":0.3266889750957489},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.24606207013130188},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.22456902265548706},{"id":"https://openalex.org/C157915830","wikidata":"https://www.wikidata.org/wiki/Q2928001","display_name":"Bubble","level":2,"score":0.0},{"id":"https://openalex.org/C129307140","wikidata":"https://www.wikidata.org/wiki/Q6795880","display_name":"Maximum bubble pressure method","level":3,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/3572919","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3572919","pdf_url":null,"source":{"id":"https://openalex.org/S105046310","display_name":"ACM Transactions on Design Automation of Electronic Systems","issn_l":"1084-4309","issn":["1084-4309","1557-7309"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319798","host_organization_name":"Association for Computing Machinery","host_organization_lineage":["https://openalex.org/P4310319798"],"host_organization_lineage_names":["Association for Computing Machinery"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"ACM Transactions on Design Automation of Electronic Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","score":0.5199999809265137,"display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":25,"referenced_works":["https://openalex.org/W1479699553","https://openalex.org/W1980891674","https://openalex.org/W1981220134","https://openalex.org/W2003312212","https://openalex.org/W2041420601","https://openalex.org/W2044206819","https://openalex.org/W2047684617","https://openalex.org/W2048588974","https://openalex.org/W2078719134","https://openalex.org/W2084007230","https://openalex.org/W2101022290","https://openalex.org/W2102449048","https://openalex.org/W2112753327","https://openalex.org/W2115172404","https://openalex.org/W2129513794","https://openalex.org/W2147539449","https://openalex.org/W2161264993","https://openalex.org/W2535323484","https://openalex.org/W2798660437","https://openalex.org/W2951094271","https://openalex.org/W2983532630","https://openalex.org/W2996954354","https://openalex.org/W2999811406","https://openalex.org/W3150290710","https://openalex.org/W4200394007"],"related_works":["https://openalex.org/W2019238062","https://openalex.org/W3008068282","https://openalex.org/W2155373950","https://openalex.org/W4243618206","https://openalex.org/W2587873888","https://openalex.org/W2138825797","https://openalex.org/W3029446734","https://openalex.org/W773491645","https://openalex.org/W1993089791","https://openalex.org/W1979982061"],"abstract_inverted_index":{"Non-volatile":[0],"memory":[1,16,27,43,53,88,102,114,129,170,216],"has":[2],"been":[3],"extensively":[4],"researched":[5],"as":[6],"the":[7,14,26,80,84,91,94,127,133,152,156,160,193,200],"alternative":[8],"for":[9,24,86,105,150,214,227],"a":[10,51,63,100,168],"DRAM-based":[11,96],"system;":[12],"however,":[13],"traditional":[15],"controller":[17,81,130],"cannot":[18],"efficiently":[19,184],"track":[20],"and":[21,37,107,155,174,188],"schedule":[22],"operations":[23],"all":[25],"devices":[28],"in":[29,90],"heterogeneous":[30,189],"systems":[31],"due":[32],"to":[33,75,82,108,126],"different":[34],"timing":[35],"requirements":[36],"complex":[38],"architecture":[39,54],"supports":[40],"of":[41,202],"various":[42],"technologies.":[44],"To":[45],"address":[46],"this":[47],"issue,":[48],"we":[49],"propose":[50,139],"hybrid":[52,215],"framework":[55,164],"called":[56],"POMI":[57,98,182],"(POlling-based":[58],"Memory":[59,73],"Interface).":[60],"It":[61],"uses":[62,99],"small":[64],"buffer":[65,117],"chip":[66,118],"inserted":[67],"on":[68,119,207,225],"each":[69,120],"DIMM":[70,121],"(Dual":[71],"In-line":[72],"Module)":[74],"decouple":[76],"operation":[77],"scheduling":[78],"from":[79],"enable":[83],"support":[85,185],"diverse":[87],"technologies":[89],"system.":[92],"Unlike":[93],"conventional":[95,194],"system,":[97,171],"polling-based":[101],"bus":[103,111,148],"protocol":[104],"communication":[106],"resolve":[109],"any":[110],"conflicts":[112],"between":[113],"modules.":[115],"The":[116,143,163],"will":[122],"provide":[123],"feedback":[124,153],"information":[125],"main":[128],"so":[131],"that":[132,181],"polling":[134],"overhead":[135],"is":[136],"trivial.":[137],"We":[138],"two":[140],"unique":[141],"designs.":[142],"first":[144],"one":[145,158],"adds":[146],"additional":[147],"lines":[149],"sending":[151],"information,":[154],"second":[157],"utilizes":[159],"Command/Address":[161],"bus.":[162],"provides":[165],"several":[166],"benefits:":[167],"technology-independent":[169],"higher":[172],"parallelism,":[173],"better":[175],"scalability.":[176],"Our":[177],"experimental":[178],"results":[179],"show":[180],"can":[183],"both":[186],"homogeneous":[187],"systems.":[190],"Compared":[191,209],"with":[192,210],"DDR4-2400":[195],"implementation,":[196],"our":[197],"scheme":[198],"improves":[199,221],"performance":[201,222],"memory-intensive":[203,228],"workloads":[204],"by":[205,223],"3.7%":[206],"average.":[208],"an":[211],"existing":[212],"interface":[213],"systems,":[217],"Twin-Load,":[218],"it":[219],"also":[220],"22.0%":[224],"average":[226],"workloads.":[229]},"counts_by_year":[],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}