{"id":"https://openalex.org/W4318685218","doi":"https://doi.org/10.1145/3566097.3567894","title":"Area-Driven FPGA Logic Synthesis Using Reinforcement Learning","display_name":"Area-Driven FPGA Logic Synthesis Using Reinforcement Learning","publication_year":2023,"publication_date":"2023-01-16","ids":{"openalex":"https://openalex.org/W4318685218","doi":"https://doi.org/10.1145/3566097.3567894"},"language":"en","primary_location":{"id":"doi:10.1145/3566097.3567894","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3566097.3567894","pdf_url":null,"source":{"id":"https://openalex.org/S4363608968","display_name":"Proceedings of the 28th Asia and South Pacific Design Automation Conference","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 28th Asia and South Pacific Design Automation Conference","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5053000782","display_name":"Guanglei Zhou","orcid":"https://orcid.org/0000-0002-7434-5808"},"institutions":[{"id":"https://openalex.org/I185261750","display_name":"University of Toronto","ror":"https://ror.org/03dbr7087","country_code":"CA","type":"education","lineage":["https://openalex.org/I185261750"]}],"countries":["CA"],"is_corresponding":true,"raw_author_name":"Guanglei Zhou","raw_affiliation_strings":["University of Toronto, Toronto, Canada"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Toronto, Toronto, Canada","institution_ids":["https://openalex.org/I185261750"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5102812429","display_name":"Jason H. Anderson","orcid":"https://orcid.org/0000-0001-9083-6853"},"institutions":[{"id":"https://openalex.org/I185261750","display_name":"University of Toronto","ror":"https://ror.org/03dbr7087","country_code":"CA","type":"education","lineage":["https://openalex.org/I185261750"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Jason H. Anderson","raw_affiliation_strings":["University of Toronto, Toronto, Canada"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Toronto, Toronto, Canada","institution_ids":["https://openalex.org/I185261750"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5053000782"],"corresponding_institution_ids":["https://openalex.org/I185261750"],"apc_list":null,"apc_paid":null,"fwci":6.178,"has_fulltext":false,"cited_by_count":13,"citation_normalized_percentile":{"value":0.96788991,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":96,"max":99},"biblio":{"volume":null,"issue":null,"first_page":"159","last_page":"165"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11975","display_name":"Evolutionary Algorithms and Applications","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9957000017166138,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/netlist","display_name":"Netlist","score":0.8782609701156616},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7213320136070251},{"id":"https://openalex.org/keywords/reinforcement-learning","display_name":"Reinforcement learning","score":0.7191881537437439},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.554352879524231},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.4835069477558136},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.4198017120361328},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.38791584968566895},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.12342643737792969},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.0885319709777832}],"concepts":[{"id":"https://openalex.org/C177650935","wikidata":"https://www.wikidata.org/wiki/Q1760303","display_name":"Netlist","level":2,"score":0.8782609701156616},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7213320136070251},{"id":"https://openalex.org/C97541855","wikidata":"https://www.wikidata.org/wiki/Q830687","display_name":"Reinforcement learning","level":2,"score":0.7191881537437439},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.554352879524231},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.4835069477558136},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.4198017120361328},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.38791584968566895},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.12342643737792969},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.0885319709777832},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/3566097.3567894","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3566097.3567894","pdf_url":null,"source":{"id":"https://openalex.org/S4363608968","display_name":"Proceedings of the 28th Asia and South Pacific Design Automation Conference","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 28th Asia and South Pacific Design Automation Conference","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":7,"referenced_works":["https://openalex.org/W2076337359","https://openalex.org/W2111945398","https://openalex.org/W2145339207","https://openalex.org/W3013938122","https://openalex.org/W3109579920","https://openalex.org/W4239323126","https://openalex.org/W6669402789"],"related_works":["https://openalex.org/W2170314243","https://openalex.org/W2119179026","https://openalex.org/W2794947590","https://openalex.org/W2114971758","https://openalex.org/W2109932036","https://openalex.org/W2093081283","https://openalex.org/W4313118781","https://openalex.org/W4243305727","https://openalex.org/W2145339442","https://openalex.org/W3217774925"],"abstract_inverted_index":{"Logic":[0],"synthesis":[1,170],"involves":[2],"a":[3,11,15,28,39,52,65,173],"rich":[4],"set":[5,71,124,136],"of":[6,31,42,55,72,125,137,175],"optimization":[7],"algorithms":[8,33,56],"applied":[9],"in":[10],"specific":[12],"sequence":[13],"to":[14,19,26,35,50,68,75,100,119,164],"circuit":[16],"netlist":[17],"prior":[18],"technology":[20],"mapping.":[21],"A":[22],"conventional":[23,95,154],"approach":[24,96],"is":[25,62,162],"apply":[27,46,116],"fixed":[29],"\"recipe\"":[30],"such":[32],"deemed":[34],"work":[36],"well":[37],"for":[38,57],"wide":[40],"range":[41],"different":[43],"circuits.":[44,139,176],"We":[45,79],"reinforcement":[47],"learning":[48,82],"(RL)":[49],"determine":[51],"unique":[53],"recipe":[54],"each":[58],"circuit.":[59],"Feature-importance":[60],"analysis":[61],"conducted":[63],"using":[64],"random-forest":[66],"classifier":[67],"prune":[69],"the":[70,76,84,94,117,122,146,153,159],"features":[73],"visible":[74],"RL":[77,85,109,147,160],"agent.":[78],"demonstrate":[80],"conclusive":[81],"by":[83],"agent":[86,110,118,148,161],"and":[87,103,114,132,166],"show":[88],"significant":[89],"FPGA":[90],"area":[91],"reductions":[92],"vs.":[93],"(resyn2).":[97],"In":[98,140],"addition":[99],"circuit-by-circuit":[101],"training":[102],"inference,":[104],"we":[105,143],"also":[106],"train":[107],"an":[108,134],"on":[111,127],"multiple":[112],"circuits,":[113],"then":[115],"optimize:":[120],"1)":[121],"same":[123],"circuits":[126],"which":[128],"it":[129],"was":[130],"trained,":[131],"2)":[133],"alternative":[135],"\"unseen\"":[138],"both":[141],"scenarios,":[142],"observe":[144],"that":[145,158],"produces":[149],"higher-quality":[150],"implementations":[151],"than":[152],"approach.":[155],"This":[156],"shows":[157],"able":[163],"generalize,":[165],"perform":[167],"beneficial":[168],"logic":[169],"optimizations":[171],"across":[172],"variety":[174]},"counts_by_year":[{"year":2026,"cited_by_count":2},{"year":2025,"cited_by_count":3},{"year":2024,"cited_by_count":5},{"year":2023,"cited_by_count":3}],"updated_date":"2026-05-15T08:27:34.491423","created_date":"2025-10-10T00:00:00"}