{"id":"https://openalex.org/W4386903450","doi":"https://doi.org/10.1145/3565053.3565060","title":"Hybrid Refresh: Improving DRAM Performance by Handling Weak Rows Smartly","display_name":"Hybrid Refresh: Improving DRAM Performance by Handling Weak Rows Smartly","publication_year":2022,"publication_date":"2022-10-03","ids":{"openalex":"https://openalex.org/W4386903450","doi":"https://doi.org/10.1145/3565053.3565060"},"language":"en","primary_location":{"id":"doi:10.1145/3565053.3565060","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3565053.3565060","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2022 International Symposium on Memory Systems","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5007918862","display_name":"Samiksha Verma","orcid":null},"institutions":[{"id":"https://openalex.org/I119241673","display_name":"Indian Institute of Technology Ropar","ror":"https://ror.org/02qkhhn56","country_code":"IN","type":"education","lineage":["https://openalex.org/I119241673"]}],"countries":["IN"],"is_corresponding":true,"raw_author_name":"Samiksha Verma","raw_affiliation_strings":["CSE, Indian Institute of Technology Ropar, India, India"],"affiliations":[{"raw_affiliation_string":"CSE, Indian Institute of Technology Ropar, India, India","institution_ids":["https://openalex.org/I119241673"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5048526628","display_name":"Shirshendu Das","orcid":"https://orcid.org/0000-0002-9232-4306"},"institutions":[{"id":"https://openalex.org/I119241673","display_name":"Indian Institute of Technology Ropar","ror":"https://ror.org/02qkhhn56","country_code":"IN","type":"education","lineage":["https://openalex.org/I119241673"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Shirshendu Das","raw_affiliation_strings":["CSE, Indian Institute of Technology Ropar, India"],"affiliations":[{"raw_affiliation_string":"CSE, Indian Institute of Technology Ropar, India","institution_ids":["https://openalex.org/I119241673"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5040784884","display_name":"Vipul Bondre","orcid":null},"institutions":[{"id":"https://openalex.org/I119241673","display_name":"Indian Institute of Technology Ropar","ror":"https://ror.org/02qkhhn56","country_code":"IN","type":"education","lineage":["https://openalex.org/I119241673"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Vipul Bondre","raw_affiliation_strings":["CSE, Indian Institute of Technology Ropar, India"],"affiliations":[{"raw_affiliation_string":"CSE, Indian Institute of Technology Ropar, India","institution_ids":["https://openalex.org/I119241673"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5007918862"],"corresponding_institution_ids":["https://openalex.org/I119241673"],"apc_list":null,"apc_paid":null,"fwci":0.4541,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.63037409,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":95},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"11"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9976000189781189,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/dram","display_name":"Dram","score":0.9155044555664062},{"id":"https://openalex.org/keywords/row","display_name":"Row","score":0.8269531726837158},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7108853459358215},{"id":"https://openalex.org/keywords/throughput","display_name":"Throughput","score":0.5035070776939392},{"id":"https://openalex.org/keywords/cas-latency","display_name":"CAS latency","score":0.5017013549804688},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4899417757987976},{"id":"https://openalex.org/keywords/refresh-rate","display_name":"Refresh rate","score":0.4653730094432831},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.4577876329421997},{"id":"https://openalex.org/keywords/overhead","display_name":"Overhead (engineering)","score":0.4506979286670685},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.4342382550239563},{"id":"https://openalex.org/keywords/memory-refresh","display_name":"Memory refresh","score":0.42646434903144836},{"id":"https://openalex.org/keywords/block","display_name":"Block (permutation group theory)","score":0.4242570698261261},{"id":"https://openalex.org/keywords/memory-controller","display_name":"Memory controller","score":0.28252512216567993},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.2072291374206543},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.19422045350074768},{"id":"https://openalex.org/keywords/computer-memory","display_name":"Computer memory","score":0.11153492331504822},{"id":"https://openalex.org/keywords/database","display_name":"Database","score":0.10423398017883301}],"concepts":[{"id":"https://openalex.org/C7366592","wikidata":"https://www.wikidata.org/wiki/Q1255620","display_name":"Dram","level":2,"score":0.9155044555664062},{"id":"https://openalex.org/C135598885","wikidata":"https://www.wikidata.org/wiki/Q1366302","display_name":"Row","level":2,"score":0.8269531726837158},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7108853459358215},{"id":"https://openalex.org/C157764524","wikidata":"https://www.wikidata.org/wiki/Q1383412","display_name":"Throughput","level":3,"score":0.5035070776939392},{"id":"https://openalex.org/C189930140","wikidata":"https://www.wikidata.org/wiki/Q1112878","display_name":"CAS latency","level":4,"score":0.5017013549804688},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4899417757987976},{"id":"https://openalex.org/C109034871","wikidata":"https://www.wikidata.org/wiki/Q949326","display_name":"Refresh rate","level":2,"score":0.4653730094432831},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.4577876329421997},{"id":"https://openalex.org/C2779960059","wikidata":"https://www.wikidata.org/wiki/Q7113681","display_name":"Overhead (engineering)","level":2,"score":0.4506979286670685},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.4342382550239563},{"id":"https://openalex.org/C87907426","wikidata":"https://www.wikidata.org/wiki/Q6815755","display_name":"Memory refresh","level":4,"score":0.42646434903144836},{"id":"https://openalex.org/C2777210771","wikidata":"https://www.wikidata.org/wiki/Q4927124","display_name":"Block (permutation group theory)","level":2,"score":0.4242570698261261},{"id":"https://openalex.org/C100800780","wikidata":"https://www.wikidata.org/wiki/Q1175867","display_name":"Memory controller","level":3,"score":0.28252512216567993},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.2072291374206543},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.19422045350074768},{"id":"https://openalex.org/C92855701","wikidata":"https://www.wikidata.org/wiki/Q5830907","display_name":"Computer memory","level":3,"score":0.11153492331504822},{"id":"https://openalex.org/C77088390","wikidata":"https://www.wikidata.org/wiki/Q8513","display_name":"Database","level":1,"score":0.10423398017883301},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C555944384","wikidata":"https://www.wikidata.org/wiki/Q249","display_name":"Wireless","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/3565053.3565060","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3565053.3565060","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2022 International Symposium on Memory Systems","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":29,"referenced_works":["https://openalex.org/W1578894366","https://openalex.org/W2030743268","https://openalex.org/W2031870500","https://openalex.org/W2034861439","https://openalex.org/W2036853599","https://openalex.org/W2040767245","https://openalex.org/W2105680229","https://openalex.org/W2119092821","https://openalex.org/W2124608923","https://openalex.org/W2130154972","https://openalex.org/W2144005128","https://openalex.org/W2144154231","https://openalex.org/W2157116240","https://openalex.org/W2166263440","https://openalex.org/W2193198328","https://openalex.org/W2256393748","https://openalex.org/W2529008862","https://openalex.org/W2626519144","https://openalex.org/W2762750764","https://openalex.org/W2911338367","https://openalex.org/W2953044030","https://openalex.org/W2999623539","https://openalex.org/W3004383742","https://openalex.org/W3043188845","https://openalex.org/W3215634574","https://openalex.org/W4232168013","https://openalex.org/W4245783794","https://openalex.org/W4251362763","https://openalex.org/W4255078785"],"related_works":["https://openalex.org/W4293430534","https://openalex.org/W2342813629","https://openalex.org/W3150934690","https://openalex.org/W4297812927","https://openalex.org/W2335743642","https://openalex.org/W2800412005","https://openalex.org/W4255078785","https://openalex.org/W3022841333","https://openalex.org/W2049504176","https://openalex.org/W2080488045"],"abstract_inverted_index":{"Modern":[0],"memory":[1,36],"systems":[2],"use":[3],"DRAM":[4,18,53,90],"as":[5,86],"their":[6,31],"basic":[7],"building":[8],"block":[9],"due":[10],"to":[11,25,29,57],"its":[12],"low":[13],"cost":[14],"per":[15,87],"bit":[16],"property.":[17],"cells":[19],"are":[20,67,103],"leaky":[21],"and":[22,42],"they":[23,102],"need":[24,72],"be":[26],"refreshed":[27],"periodically":[28],"retain":[30],"data.":[32,117],"Refresh":[33],"operation":[34],"degrades":[35],"throughput":[37],"by":[38,108],"adding":[39],"extra":[40],"latency":[41],"eats":[43],"up":[44],"significant":[45],"power.":[46],"The":[47],"refresh":[48,73,91,99],"rate":[49],"of":[50,61],"the":[51,58,62,84,88],"overall":[52],"is":[54,79],"decided":[55],"according":[56],"retention":[59],"time":[60],"weakest":[63],"row.":[64],"Although":[65],"there":[66],"very":[68],"few":[69],"rows":[70,85,111],"that":[71],"at":[74],"a":[75],"high":[76],"rate,":[77],"it":[78],"kept":[80],"same":[81],"for":[82],"all":[83],"standard":[89],"technique.":[92],"Many":[93],"existing":[94],"papers":[95],"work":[96],"on":[97],"reducing":[98],"overhead,":[100],"but":[101],"compromising":[104],"with":[105,115],"space":[106],"either":[107],"discarding":[109],"weak":[110],"or":[112],"populating":[113],"them":[114],"duplicate":[116]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2024,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
