{"id":"https://openalex.org/W4318256778","doi":"https://doi.org/10.1145/3559009.3569688","title":"MLIR Loop Optimizations for High-Level Synthesis","display_name":"MLIR Loop Optimizations for High-Level Synthesis","publication_year":2022,"publication_date":"2022-10-08","ids":{"openalex":"https://openalex.org/W4318256778","doi":"https://doi.org/10.1145/3559009.3569688"},"language":"en","primary_location":{"id":"doi:10.1145/3559009.3569688","is_oa":true,"landing_page_url":"http://dx.doi.org/10.1145/3559009.3569688","pdf_url":"https://dl.acm.org/doi/pdf/10.1145/3559009.3569688","source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the International Conference on Parallel Architectures and Compilation Techniques","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"gold","oa_url":"https://dl.acm.org/doi/pdf/10.1145/3559009.3569688","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5033121816","display_name":"Serena Curzel","orcid":"https://orcid.org/0000-0002-8202-1627"},"institutions":[{"id":"https://openalex.org/I93860229","display_name":"Politecnico di Milano","ror":"https://ror.org/01nffqt88","country_code":"IT","type":"education","lineage":["https://openalex.org/I93860229"]}],"countries":["IT"],"is_corresponding":true,"raw_author_name":"Serena Curzel","raw_affiliation_strings":["Politecnico di Milano, Milano, Italy"],"affiliations":[{"raw_affiliation_string":"Politecnico di Milano, Milano, Italy","institution_ids":["https://openalex.org/I93860229"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5011019468","display_name":"Sofija Jovic","orcid":"https://orcid.org/0000-0003-2061-0802"},"institutions":[{"id":"https://openalex.org/I93860229","display_name":"Politecnico di Milano","ror":"https://ror.org/01nffqt88","country_code":"IT","type":"education","lineage":["https://openalex.org/I93860229"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Sofija Jovic","raw_affiliation_strings":["Politecnico di Milano, Milano, Italy"],"affiliations":[{"raw_affiliation_string":"Politecnico di Milano, Milano, Italy","institution_ids":["https://openalex.org/I93860229"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5008177871","display_name":"Michele Fiorito","orcid":"https://orcid.org/0000-0001-8675-6703"},"institutions":[{"id":"https://openalex.org/I93860229","display_name":"Politecnico di Milano","ror":"https://ror.org/01nffqt88","country_code":"IT","type":"education","lineage":["https://openalex.org/I93860229"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Michele Fiorito","raw_affiliation_strings":["Politecnico di Milano, Milano, Italy"],"affiliations":[{"raw_affiliation_string":"Politecnico di Milano, Milano, Italy","institution_ids":["https://openalex.org/I93860229"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5041853964","display_name":"Antonino Tumeo","orcid":"https://orcid.org/0000-0001-9452-120X"},"institutions":[{"id":"https://openalex.org/I93860229","display_name":"Politecnico di Milano","ror":"https://ror.org/01nffqt88","country_code":"IT","type":"education","lineage":["https://openalex.org/I93860229"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Antonino Tumeo","raw_affiliation_strings":["PNNL","Politecnico di Milano Milano, Italy","PNNL Richland, Washington, USA"],"affiliations":[{"raw_affiliation_string":"PNNL","institution_ids":[]},{"raw_affiliation_string":"Politecnico di Milano Milano, Italy","institution_ids":["https://openalex.org/I93860229"]},{"raw_affiliation_string":"PNNL Richland, Washington, USA","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5028565685","display_name":"Fabrizio Ferrandi","orcid":"https://orcid.org/0000-0003-0301-4419"},"institutions":[{"id":"https://openalex.org/I93860229","display_name":"Politecnico di Milano","ror":"https://ror.org/01nffqt88","country_code":"IT","type":"education","lineage":["https://openalex.org/I93860229"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Fabrizio Ferrandi","raw_affiliation_strings":["Politecnico di Milano, Milano, Italy"],"affiliations":[{"raw_affiliation_string":"Politecnico di Milano, Milano, Italy","institution_ids":["https://openalex.org/I93860229"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5033121816"],"corresponding_institution_ids":["https://openalex.org/I93860229"],"apc_list":null,"apc_paid":null,"fwci":0.4668,"has_fulltext":true,"cited_by_count":2,"citation_normalized_percentile":{"value":0.63189082,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":94,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"544","last_page":"545"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9966999888420105,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8628453016281128},{"id":"https://openalex.org/keywords/high-level-synthesis","display_name":"High-level synthesis","score":0.7533106803894043},{"id":"https://openalex.org/keywords/compiler","display_name":"Compiler","score":0.7127809524536133},{"id":"https://openalex.org/keywords/hardware-description-language","display_name":"Hardware description language","score":0.6360045671463013},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.6339364647865295},{"id":"https://openalex.org/keywords/verilog","display_name":"Verilog","score":0.6201786994934082},{"id":"https://openalex.org/keywords/vhdl","display_name":"VHDL","score":0.6039794683456421},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5816047787666321},{"id":"https://openalex.org/keywords/register-transfer-level","display_name":"Register-transfer level","score":0.5147233605384827},{"id":"https://openalex.org/keywords/asynchronous-communication","display_name":"Asynchronous communication","score":0.48676419258117676},{"id":"https://openalex.org/keywords/code-generation","display_name":"Code generation","score":0.45177382230758667},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.439619779586792},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.3490578234195709},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3315110504627228},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.24768894910812378},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.17527863383293152},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.17021480202674866}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8628453016281128},{"id":"https://openalex.org/C58013763","wikidata":"https://www.wikidata.org/wiki/Q5754574","display_name":"High-level synthesis","level":3,"score":0.7533106803894043},{"id":"https://openalex.org/C169590947","wikidata":"https://www.wikidata.org/wiki/Q47506","display_name":"Compiler","level":2,"score":0.7127809524536133},{"id":"https://openalex.org/C42143788","wikidata":"https://www.wikidata.org/wiki/Q173341","display_name":"Hardware description language","level":3,"score":0.6360045671463013},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.6339364647865295},{"id":"https://openalex.org/C2779030575","wikidata":"https://www.wikidata.org/wiki/Q827773","display_name":"Verilog","level":3,"score":0.6201786994934082},{"id":"https://openalex.org/C36941000","wikidata":"https://www.wikidata.org/wiki/Q209455","display_name":"VHDL","level":3,"score":0.6039794683456421},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5816047787666321},{"id":"https://openalex.org/C34854456","wikidata":"https://www.wikidata.org/wiki/Q1484552","display_name":"Register-transfer level","level":4,"score":0.5147233605384827},{"id":"https://openalex.org/C151319957","wikidata":"https://www.wikidata.org/wiki/Q752739","display_name":"Asynchronous communication","level":2,"score":0.48676419258117676},{"id":"https://openalex.org/C133162039","wikidata":"https://www.wikidata.org/wiki/Q1061077","display_name":"Code generation","level":3,"score":0.45177382230758667},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.439619779586792},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.3490578234195709},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3315110504627228},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.24768894910812378},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.17527863383293152},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.17021480202674866},{"id":"https://openalex.org/C26517878","wikidata":"https://www.wikidata.org/wiki/Q228039","display_name":"Key (lock)","level":2,"score":0.0},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.0},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1145/3559009.3569688","is_oa":true,"landing_page_url":"http://dx.doi.org/10.1145/3559009.3569688","pdf_url":"https://dl.acm.org/doi/pdf/10.1145/3559009.3569688","source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the International Conference on Parallel Architectures and Compilation Techniques","raw_type":"proceedings-article"},{"id":"pmh:oai:re.public.polimi.it:11311/1223351","is_oa":true,"landing_page_url":"https://hdl.handle.net/11311/1223351","pdf_url":null,"source":{"id":"https://openalex.org/S4306400312","display_name":"Virtual Community of Pathological Anatomy (University of Castilla La Mancha)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I79189158","host_organization_name":"University of Castilla-La Mancha","host_organization_lineage":["https://openalex.org/I79189158"],"host_organization_lineage_names":[],"type":"repository"},"license":"other-oa","license_id":"https://openalex.org/licenses/other-oa","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"info:eu-repo/semantics/conferenceObject"}],"best_oa_location":{"id":"doi:10.1145/3559009.3569688","is_oa":true,"landing_page_url":"http://dx.doi.org/10.1145/3559009.3569688","pdf_url":"https://dl.acm.org/doi/pdf/10.1145/3559009.3569688","source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the International Conference on Parallel Architectures and Compilation Techniques","raw_type":"proceedings-article"},"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/8","score":0.5,"display_name":"Decent work and economic growth"}],"awards":[{"id":"https://openalex.org/G4656475984","display_name":null,"funder_award_id":"957269, 101004203","funder_id":"https://openalex.org/F4320338335","funder_display_name":"H2020 European Research Council"},{"id":"https://openalex.org/G5141416053","display_name":null,"funder_award_id":"957269","funder_id":"https://openalex.org/F4320332999","funder_display_name":"Horizon 2020 Framework Programme"}],"funders":[{"id":"https://openalex.org/F4320306084","display_name":"U.S. Department of Energy","ror":"https://ror.org/01bj3aw27"},{"id":"https://openalex.org/F4320332180","display_name":"Defense Advanced Research Projects Agency","ror":"https://ror.org/02caytj08"},{"id":"https://openalex.org/F4320332999","display_name":"Horizon 2020 Framework Programme","ror":"https://ror.org/00k4n6c32"},{"id":"https://openalex.org/F4320338335","display_name":"H2020 European Research Council","ror":"https://ror.org/0472cxd90"},{"id":"https://openalex.org/F4320338354","display_name":"Pacific Northwest National Laboratory","ror":"https://ror.org/05h992307"}],"has_content":{"pdf":true,"grobid_xml":true},"content_urls":{"pdf":"https://content.openalex.org/works/W4318256778.pdf","grobid_xml":"https://content.openalex.org/works/W4318256778.grobid-xml"},"referenced_works_count":3,"referenced_works":["https://openalex.org/W1519538706","https://openalex.org/W3122286897","https://openalex.org/W3212867926"],"related_works":["https://openalex.org/W2366672283","https://openalex.org/W2168113051","https://openalex.org/W4233828762","https://openalex.org/W2389932690","https://openalex.org/W2097236935","https://openalex.org/W2916312349","https://openalex.org/W2153401337","https://openalex.org/W4214657400","https://openalex.org/W2386257256","https://openalex.org/W1843355381"],"abstract_inverted_index":{"High-Level":[0],"Synthesis":[1],"(HLS)":[2],"tools":[3,88],"automatically":[4],"translate":[5],"code":[6,99],"from":[7,36],"a":[8,17],"general-purpose":[9,49,84],"programming":[10,85],"language":[11,20],"(typically":[12],"C":[13],"or":[14,25],"C++)":[15],"into":[16],"hardware":[18,30,81,102],"description":[19],"(HDL)":[21],"such":[22,63],"as":[23,64],"Verilog":[24],"VHDL,":[26],"significantly":[27],"reducing":[28],"the":[29,37,65,78,91,97],"design":[31],"productivity":[32],"gap.":[33],"HLS":[34,87],"benefits":[35],"same":[38],"compiler":[39],"optimizations":[40],"that":[41],"identify":[42],"instruction,":[43],"memory,":[44],"and":[45,70,73,83],"data":[46],"parallelism":[47],"for":[48],"processors.":[50],"However,":[51],"they":[52],"also":[53],"need":[54],"to":[55,100],"consider":[56],"specific":[57],"needs":[58],"of":[59,67,77,93],"low-level":[60],"circuit":[61],"design,":[62],"notion":[66],"time,":[68],"synchronous":[69],"asynchronous":[71],"logic,":[72],"wiring":[74],"delays.":[75],"Because":[76],"mismatch":[79],"between":[80],"abstractions":[82],"languages,":[86],"often":[89],"require":[90],"addition":[92],"pragma":[94],"directives":[95],"in":[96],"input":[98],"guide":[101],"generation.":[103]},"counts_by_year":[{"year":2024,"cited_by_count":2}],"updated_date":"2026-04-10T15:06:20.359241","created_date":"2025-10-10T00:00:00"}