{"id":"https://openalex.org/W4318256984","doi":"https://doi.org/10.1145/3557988.3569713","title":"Machine-Learning Based Delay Prediction for FPGA Technology Mapping","display_name":"Machine-Learning Based Delay Prediction for FPGA Technology Mapping","publication_year":2022,"publication_date":"2022-11-03","ids":{"openalex":"https://openalex.org/W4318256984","doi":"https://doi.org/10.1145/3557988.3569713"},"language":"en","primary_location":{"id":"doi:10.1145/3557988.3569713","is_oa":true,"landing_page_url":"https://doi.org/10.1145/3557988.3569713","pdf_url":"https://dl.acm.org/doi/pdf/10.1145/3557988.3569713","source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 24th ACM/IEEE Workshop on System Level Interconnect Pathfinding","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"gold","oa_url":"https://dl.acm.org/doi/pdf/10.1145/3557988.3569713","any_repository_has_fulltext":null},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5101627997","display_name":"Hailiang Hu","orcid":"https://orcid.org/0000-0002-3525-4604"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Hailiang Hu","raw_affiliation_strings":["Texas A&amp;M University"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Texas A&amp;M University","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100326929","display_name":"Hu Jiang","orcid":"https://orcid.org/0000-0003-2711-9995"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Jiang Hu","raw_affiliation_strings":["Texas A&amp;M University"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Texas A&amp;M University","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100403380","display_name":"Fan Zhang","orcid":"https://orcid.org/0000-0001-6087-8243"},"institutions":[{"id":"https://openalex.org/I1311921367","display_name":"Advanced Micro Devices (Canada)","ror":"https://ror.org/02yh0k313","country_code":"CA","type":"company","lineage":["https://openalex.org/I1311921367","https://openalex.org/I4210137977"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Fan Zhang","raw_affiliation_strings":["Advanced Micro Devices"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Advanced Micro Devices","institution_ids":["https://openalex.org/I1311921367"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101536130","display_name":"Tian Bing","orcid":"https://orcid.org/0000-0001-6123-0879"},"institutions":[{"id":"https://openalex.org/I1311921367","display_name":"Advanced Micro Devices (Canada)","ror":"https://ror.org/02yh0k313","country_code":"CA","type":"company","lineage":["https://openalex.org/I1311921367","https://openalex.org/I4210137977"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Bing Tian","raw_affiliation_strings":["Advanced Micro Devices"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Advanced Micro Devices","institution_ids":["https://openalex.org/I1311921367"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5080828363","display_name":"Ismail Bustany","orcid":"https://orcid.org/0000-0002-7099-1546"},"institutions":[{"id":"https://openalex.org/I1311921367","display_name":"Advanced Micro Devices (Canada)","ror":"https://ror.org/02yh0k313","country_code":"CA","type":"company","lineage":["https://openalex.org/I1311921367","https://openalex.org/I4210137977"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Ismail Bustany","raw_affiliation_strings":["Advanced Micro Devices"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Advanced Micro Devices","institution_ids":["https://openalex.org/I1311921367"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":1.1664,"has_fulltext":false,"cited_by_count":5,"citation_normalized_percentile":{"value":0.7811828,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9977999925613403,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/lookup-table","display_name":"Lookup table","score":0.795353889465332},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.78486168384552},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.6981688737869263},{"id":"https://openalex.org/keywords/heuristics","display_name":"Heuristics","score":0.6046804785728455},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.574253261089325},{"id":"https://openalex.org/keywords/estimator","display_name":"Estimator","score":0.5497826933860779},{"id":"https://openalex.org/keywords/delay-calculation","display_name":"Delay calculation","score":0.5454616546630859},{"id":"https://openalex.org/keywords/heuristic","display_name":"Heuristic","score":0.515900731086731},{"id":"https://openalex.org/keywords/logic-analyzer","display_name":"Logic analyzer","score":0.49569427967071533},{"id":"https://openalex.org/keywords/logic-block","display_name":"Logic block","score":0.4298909306526184},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.4141753315925598},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.41116097569465637},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.26282113790512085},{"id":"https://openalex.org/keywords/propagation-delay","display_name":"Propagation delay","score":0.22553035616874695},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.19728055596351624},{"id":"https://openalex.org/keywords/spectrum-analyzer","display_name":"Spectrum analyzer","score":0.10921719670295715}],"concepts":[{"id":"https://openalex.org/C134835016","wikidata":"https://www.wikidata.org/wiki/Q690265","display_name":"Lookup table","level":2,"score":0.795353889465332},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.78486168384552},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6981688737869263},{"id":"https://openalex.org/C127705205","wikidata":"https://www.wikidata.org/wiki/Q5748245","display_name":"Heuristics","level":2,"score":0.6046804785728455},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.574253261089325},{"id":"https://openalex.org/C185429906","wikidata":"https://www.wikidata.org/wiki/Q1130160","display_name":"Estimator","level":2,"score":0.5497826933860779},{"id":"https://openalex.org/C174086752","wikidata":"https://www.wikidata.org/wiki/Q5253471","display_name":"Delay calculation","level":3,"score":0.5454616546630859},{"id":"https://openalex.org/C173801870","wikidata":"https://www.wikidata.org/wiki/Q201413","display_name":"Heuristic","level":2,"score":0.515900731086731},{"id":"https://openalex.org/C188434589","wikidata":"https://www.wikidata.org/wiki/Q1478762","display_name":"Logic analyzer","level":3,"score":0.49569427967071533},{"id":"https://openalex.org/C2778325283","wikidata":"https://www.wikidata.org/wiki/Q1125244","display_name":"Logic block","level":3,"score":0.4298909306526184},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.4141753315925598},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.41116097569465637},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.26282113790512085},{"id":"https://openalex.org/C90806461","wikidata":"https://www.wikidata.org/wiki/Q1144416","display_name":"Propagation delay","level":2,"score":0.22553035616874695},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.19728055596351624},{"id":"https://openalex.org/C158007255","wikidata":"https://www.wikidata.org/wiki/Q1055222","display_name":"Spectrum analyzer","level":2,"score":0.10921719670295715},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/3557988.3569713","is_oa":true,"landing_page_url":"https://doi.org/10.1145/3557988.3569713","pdf_url":"https://dl.acm.org/doi/pdf/10.1145/3557988.3569713","source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 24th ACM/IEEE Workshop on System Level Interconnect Pathfinding","raw_type":"proceedings-article"}],"best_oa_location":{"id":"doi:10.1145/3557988.3569713","is_oa":true,"landing_page_url":"https://doi.org/10.1145/3557988.3569713","pdf_url":"https://dl.acm.org/doi/pdf/10.1145/3557988.3569713","source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 24th ACM/IEEE Workshop on System Level Interconnect Pathfinding","raw_type":"proceedings-article"},"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":13,"referenced_works":["https://openalex.org/W2021709993","https://openalex.org/W2035561773","https://openalex.org/W2105715355","https://openalex.org/W2903881552","https://openalex.org/W3018195242","https://openalex.org/W3033033241","https://openalex.org/W3043621356","https://openalex.org/W3109579920","https://openalex.org/W3174010073","https://openalex.org/W3183732142","https://openalex.org/W3197603378","https://openalex.org/W4285726874","https://openalex.org/W6675354045"],"related_works":["https://openalex.org/W2366554144","https://openalex.org/W2003435315","https://openalex.org/W2024574431","https://openalex.org/W4239932082","https://openalex.org/W2083030004","https://openalex.org/W2140645577","https://openalex.org/W2477477398","https://openalex.org/W2113469110","https://openalex.org/W21706283","https://openalex.org/W2154203817"],"abstract_inverted_index":{"Accurate":[0],"delay":[1,86,120,133],"prediction":[2],"is":[3,26,37,52],"important":[4],"in":[5],"the":[6,85,93,96,108,118,126,129],"early":[7],"stages":[8],"of":[9,87,95,124],"logic":[10,99],"and":[11,59,82],"high-level":[12],"synthesis.":[13],"In":[14,70],"technology":[15,68,101],"mapping":[16],"for":[17,80,128],"field":[18],"programmable":[19],"gate":[20],"array":[21],"(FPGA),":[22],"a":[23,29,40,48,75,88,112],"gate-level":[24,89],"circuit":[25,42,90],"transcribed":[27],"into":[28],"lookup":[30],"table":[31],"(LUT)-level":[32],"circuit.":[33],"Quick":[34],"timing":[35,50],"analysis":[36],"necessary":[38],"on":[39,137],"pre-mapped":[41],"to":[43,56,117],"guide":[44],"optimizations":[45],"downstream.":[46],"However,":[47],"static":[49],"analyzer":[51],"too":[53],"slow":[54],"due":[55],"its":[57],"complexity":[58],"highly":[60],"inaccurate":[61],"like":[62],"other":[63],"faster":[64],"empirical":[65],"heuristics":[66],"before":[67],"mapping.":[69,102],"this":[71],"work,":[72],"we":[73],"present":[74],"machine":[76],"learning":[77],"based":[78],"framework":[79],"accurately":[81],"efficiently":[83],"estimating":[84],"from":[91],"predicting":[92],"depth":[94],"corresponding":[97],"LUT":[98],"after":[100],"Our":[103],"experimental":[104],"results":[105],"show":[106],"that":[107],"proposed":[109],"method":[110],"achieves":[111],"56x":[113],"accuracy":[114],"improvement":[115],"compared":[116],"existing":[119],"estimation":[121],"heuristic.":[122],"Instead":[123],"running":[125],"mapper":[127],"ground":[130],"truth,":[131],"our":[132],"estimator":[134],"saves":[135],"87.5%":[136],"runtime":[138],"with":[139],"negligible":[140],"error.":[141]},"counts_by_year":[{"year":2025,"cited_by_count":2},{"year":2024,"cited_by_count":2},{"year":2023,"cited_by_count":1}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}
