{"id":"https://openalex.org/W4320067870","doi":"https://doi.org/10.1145/3547276.3548523","title":"Accelerating the Task Activation and Data Communication for Dataflow Computing","display_name":"Accelerating the Task Activation and Data Communication for Dataflow Computing","publication_year":2022,"publication_date":"2022-08-29","ids":{"openalex":"https://openalex.org/W4320067870","doi":"https://doi.org/10.1145/3547276.3548523"},"language":"en","primary_location":{"id":"doi:10.1145/3547276.3548523","is_oa":true,"landing_page_url":"http://dx.doi.org/10.1145/3547276.3548523","pdf_url":"https://dl.acm.org/doi/pdf/10.1145/3547276.3548523?download=true","source":null,"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Workshop Proceedings of the 51st International Conference on Parallel Processing","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"gold","oa_url":"https://dl.acm.org/doi/pdf/10.1145/3547276.3548523?download=true","any_repository_has_fulltext":null},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5100511630","display_name":"Du Zheng","orcid":null},"institutions":[{"id":"https://openalex.org/I99065089","display_name":"Tsinghua University","ror":"https://ror.org/03cve4549","country_code":"CN","type":"education","lineage":["https://openalex.org/I99065089"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Du Zheng","raw_affiliation_strings":["Department of Computer Science and Technology, Tsinghua University, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computer Science and Technology, Tsinghua University, China","institution_ids":["https://openalex.org/I99065089"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100537874","display_name":"Wenjie Zhao","orcid":"https://orcid.org/0009-0002-7416-7164"},"institutions":[{"id":"https://openalex.org/I180726961","display_name":"Shenzhen University","ror":"https://ror.org/01vy4gh70","country_code":"CN","type":"education","lineage":["https://openalex.org/I180726961"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Zhao Wenjie","raw_affiliation_strings":["College of Computer Science and Software Engineering, Shenzhen University, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"College of Computer Science and Software Engineering, Shenzhen University, China","institution_ids":["https://openalex.org/I180726961"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5102351728","display_name":"Zhiwei Wen","orcid":null},"institutions":[{"id":"https://openalex.org/I180726961","display_name":"Shenzhen University","ror":"https://ror.org/01vy4gh70","country_code":"CN","type":"education","lineage":["https://openalex.org/I180726961"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Wen Zhiwei","raw_affiliation_strings":["College of Computer Science and Software Engineering, Shenzhen University, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"College of Computer Science and Software Engineering, Shenzhen University, China","institution_ids":["https://openalex.org/I180726961"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5101064077","display_name":"Luo Qiuming","orcid":null},"institutions":[{"id":"https://openalex.org/I180726961","display_name":"Shenzhen University","ror":"https://ror.org/01vy4gh70","country_code":"CN","type":"education","lineage":["https://openalex.org/I180726961"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Luo Qiuming","raw_affiliation_strings":["College of Computer Science and Software Engineering, Shenzhen University, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"College of Computer Science and Software Engineering, Shenzhen University, China","institution_ids":["https://openalex.org/I180726961"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.2333,"has_fulltext":true,"cited_by_count":2,"citation_normalized_percentile":{"value":0.54892473,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":98},"biblio":{"volume":"50","issue":null,"first_page":"1","last_page":"7"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9970999956130981,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/dataflow","display_name":"Dataflow","score":0.986003041267395},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8340831398963928},{"id":"https://openalex.org/keywords/dataflow-architecture","display_name":"Dataflow architecture","score":0.7084320187568665},{"id":"https://openalex.org/keywords/von-neumann-architecture","display_name":"Von Neumann architecture","score":0.7066409587860107},{"id":"https://openalex.org/keywords/data-flow-diagram","display_name":"Data flow diagram","score":0.6854903101921082},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.646817147731781},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.5828226804733276},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5158485770225525},{"id":"https://openalex.org/keywords/task","display_name":"Task (project management)","score":0.5072126388549805},{"id":"https://openalex.org/keywords/implementation","display_name":"Implementation","score":0.5016860961914062},{"id":"https://openalex.org/keywords/graph","display_name":"Graph","score":0.47646069526672363},{"id":"https://openalex.org/keywords/synchronization","display_name":"Synchronization (alternating current)","score":0.463407963514328},{"id":"https://openalex.org/keywords/multi-core-processor","display_name":"Multi-core processor","score":0.4608153700828552},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3895485997200012},{"id":"https://openalex.org/keywords/distributed-computing","display_name":"Distributed computing","score":0.3464411199092865},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.15928915143013},{"id":"https://openalex.org/keywords/theoretical-computer-science","display_name":"Theoretical computer science","score":0.15227049589157104},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.09661409258842468},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.08168110251426697}],"concepts":[{"id":"https://openalex.org/C96324660","wikidata":"https://www.wikidata.org/wiki/Q205446","display_name":"Dataflow","level":2,"score":0.986003041267395},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8340831398963928},{"id":"https://openalex.org/C176727019","wikidata":"https://www.wikidata.org/wiki/Q1172415","display_name":"Dataflow architecture","level":3,"score":0.7084320187568665},{"id":"https://openalex.org/C80469333","wikidata":"https://www.wikidata.org/wiki/Q189088","display_name":"Von Neumann architecture","level":2,"score":0.7066409587860107},{"id":"https://openalex.org/C489000","wikidata":"https://www.wikidata.org/wiki/Q747385","display_name":"Data flow diagram","level":2,"score":0.6854903101921082},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.646817147731781},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.5828226804733276},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5158485770225525},{"id":"https://openalex.org/C2780451532","wikidata":"https://www.wikidata.org/wiki/Q759676","display_name":"Task (project management)","level":2,"score":0.5072126388549805},{"id":"https://openalex.org/C26713055","wikidata":"https://www.wikidata.org/wiki/Q245962","display_name":"Implementation","level":2,"score":0.5016860961914062},{"id":"https://openalex.org/C132525143","wikidata":"https://www.wikidata.org/wiki/Q141488","display_name":"Graph","level":2,"score":0.47646069526672363},{"id":"https://openalex.org/C2778562939","wikidata":"https://www.wikidata.org/wiki/Q1298791","display_name":"Synchronization (alternating current)","level":3,"score":0.463407963514328},{"id":"https://openalex.org/C78766204","wikidata":"https://www.wikidata.org/wiki/Q555032","display_name":"Multi-core processor","level":2,"score":0.4608153700828552},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3895485997200012},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.3464411199092865},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.15928915143013},{"id":"https://openalex.org/C80444323","wikidata":"https://www.wikidata.org/wiki/Q2878974","display_name":"Theoretical computer science","level":1,"score":0.15227049589157104},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.09661409258842468},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.08168110251426697},{"id":"https://openalex.org/C127162648","wikidata":"https://www.wikidata.org/wiki/Q16858953","display_name":"Channel (broadcasting)","level":2,"score":0.0},{"id":"https://openalex.org/C187736073","wikidata":"https://www.wikidata.org/wiki/Q2920921","display_name":"Management","level":1,"score":0.0},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0},{"id":"https://openalex.org/C77088390","wikidata":"https://www.wikidata.org/wiki/Q8513","display_name":"Database","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/3547276.3548523","is_oa":true,"landing_page_url":"http://dx.doi.org/10.1145/3547276.3548523","pdf_url":"https://dl.acm.org/doi/pdf/10.1145/3547276.3548523?download=true","source":null,"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Workshop Proceedings of the 51st International Conference on Parallel Processing","raw_type":"proceedings-article"}],"best_oa_location":{"id":"doi:10.1145/3547276.3548523","is_oa":true,"landing_page_url":"http://dx.doi.org/10.1145/3547276.3548523","pdf_url":"https://dl.acm.org/doi/pdf/10.1145/3547276.3548523?download=true","source":null,"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Workshop Proceedings of the 51st International Conference on Parallel Processing","raw_type":"proceedings-article"},"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy","score":0.46000000834465027}],"awards":[],"funders":[],"has_content":{"pdf":true,"grobid_xml":true},"content_urls":{"pdf":"https://content.openalex.org/works/W4320067870.pdf","grobid_xml":"https://content.openalex.org/works/W4320067870.grobid-xml"},"referenced_works_count":15,"referenced_works":["https://openalex.org/W1535111405","https://openalex.org/W1983394510","https://openalex.org/W1996138408","https://openalex.org/W2070353846","https://openalex.org/W2100092435","https://openalex.org/W2136453233","https://openalex.org/W2137380783","https://openalex.org/W2142501475","https://openalex.org/W2149135813","https://openalex.org/W2157373341","https://openalex.org/W2173213060","https://openalex.org/W2612076670","https://openalex.org/W2998570630","https://openalex.org/W4250427650","https://openalex.org/W6619900983"],"related_works":["https://openalex.org/W1894511976","https://openalex.org/W1998949396","https://openalex.org/W2029462071","https://openalex.org/W4320067870","https://openalex.org/W2356887951","https://openalex.org/W3003815297","https://openalex.org/W2368301563","https://openalex.org/W4365802058","https://openalex.org/W172366259","https://openalex.org/W1534157463"],"abstract_inverted_index":{"The":[0,95],"hybrid":[1,43],"dataflow/von-Neumann":[2,44],"[1]":[3],"architectures":[4],"may":[5],"differ":[6],"in":[7],"implementations":[8],"but":[9],"all":[10],"follow":[11],"similar":[12],"principles:":[13],"they":[14],"harness":[15],"the":[16,23,28,31,68,77,88,93,100,107,112,122],"parallelism":[17],"and":[18,52,75,91,121],"data":[19,109],"synchronization":[20],"inherent":[21],"to":[22],"dataflow":[24],"model,":[25],"yet":[26],"maintain":[27],"programmability":[29],"of":[30,42,114],"von-Neumann":[32],"model.":[33],"In":[34],"this":[35],"paper,":[36],"we":[37,60,83],"raise":[38],"a":[39],"new":[40],"kind":[41],"architectures,":[45],"which":[46,59],"contains":[47],"TAU":[48],"(Task":[49],"Activated":[50],"Unit)":[51],"SPM":[53],"[9]":[54],"(scratchpad":[55],"memory)":[56],"components,":[57],"by":[58,104,119],"can":[61],"enhance":[62],"parallel":[63],"efficiency.":[64],"We":[65],"also":[66],"implement":[67],"prototype":[69],"design,":[70],"integrated":[71],"with":[72],"peripheral":[73],"devices":[74],"verify":[76],"whole":[78],"system":[79,86,90],"on":[80,87],"FPGA.":[81],"Finally,":[82],"deploy":[84],"operating":[85],"hardware":[89,123],"profile":[92],"performance.":[94],"experimental":[96],"results":[97],"show":[98],"that":[99],"performance":[101,113],"is":[102,117,126],"improved":[103,118],"3.07%\u223c10.32%":[105],"under":[106],"random":[108],"flow":[110],"graph,":[111],"inter-core":[115],"communication":[116],"4%":[120],"acceleration":[124],"effect":[125],"achieved.":[127]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2024,"cited_by_count":1}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}
