{"id":"https://openalex.org/W4319870559","doi":"https://doi.org/10.1145/3543622.3578888","title":"FPGAs and Their Evolving Role in Domain Specific Architectures","display_name":"FPGAs and Their Evolving Role in Domain Specific Architectures","publication_year":2023,"publication_date":"2023-02-10","ids":{"openalex":"https://openalex.org/W4319870559","doi":"https://doi.org/10.1145/3543622.3578888"},"language":"en","primary_location":{"id":"doi:10.1145/3543622.3578888","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3543622.3578888","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2023 ACM/SIGDA International Symposium on Field Programmable Gate Arrays","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5050847957","display_name":"Jaideep Dastidar","orcid":"https://orcid.org/0000-0003-4851-3350"},"institutions":[{"id":"https://openalex.org/I4210137977","display_name":"Advanced Micro Devices (United States)","ror":"https://ror.org/04kd6c783","country_code":"US","type":"company","lineage":["https://openalex.org/I4210137977"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Jaideep Dastidar","raw_affiliation_strings":["Advanced Micro Devices (AMD), Santa Clara, CA, USA"],"raw_orcid":"https://orcid.org/0000-0003-4851-3350","affiliations":[{"raw_affiliation_string":"Advanced Micro Devices (AMD), Santa Clara, CA, USA","institution_ids":["https://openalex.org/I4210137977"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":["https://openalex.org/A5050847957"],"corresponding_institution_ids":["https://openalex.org/I4210137977"],"apc_list":null,"apc_paid":null,"fwci":0.8977,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.67784212,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":98},"biblio":{"volume":null,"issue":null,"first_page":"151","last_page":"151"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9878000020980835,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9878000020980835,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11992","display_name":"CCD and CMOS Imaging Sensors","score":0.9549999833106995,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9438999891281128,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.8286593556404114},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7187320590019226},{"id":"https://openalex.org/keywords/acceleration","display_name":"Acceleration","score":0.7069662809371948},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.6005441546440125},{"id":"https://openalex.org/keywords/application-specific-integrated-circuit","display_name":"Application-specific integrated circuit","score":0.5791712403297424},{"id":"https://openalex.org/keywords/domain","display_name":"Domain (mathematical analysis)","score":0.5562880039215088},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5356881618499756},{"id":"https://openalex.org/keywords/focus","display_name":"Focus (optics)","score":0.4713822305202484},{"id":"https://openalex.org/keywords/hardware-acceleration","display_name":"Hardware acceleration","score":0.4536154270172119},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.447797954082489},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3394133150577545},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.23974856734275818}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.8286593556404114},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7187320590019226},{"id":"https://openalex.org/C117896860","wikidata":"https://www.wikidata.org/wiki/Q11376","display_name":"Acceleration","level":2,"score":0.7069662809371948},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.6005441546440125},{"id":"https://openalex.org/C77390884","wikidata":"https://www.wikidata.org/wiki/Q217302","display_name":"Application-specific integrated circuit","level":2,"score":0.5791712403297424},{"id":"https://openalex.org/C36503486","wikidata":"https://www.wikidata.org/wiki/Q11235244","display_name":"Domain (mathematical analysis)","level":2,"score":0.5562880039215088},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5356881618499756},{"id":"https://openalex.org/C192209626","wikidata":"https://www.wikidata.org/wiki/Q190909","display_name":"Focus (optics)","level":2,"score":0.4713822305202484},{"id":"https://openalex.org/C13164978","wikidata":"https://www.wikidata.org/wiki/Q600158","display_name":"Hardware acceleration","level":3,"score":0.4536154270172119},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.447797954082489},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3394133150577545},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.23974856734275818},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C74650414","wikidata":"https://www.wikidata.org/wiki/Q11397","display_name":"Classical mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C134306372","wikidata":"https://www.wikidata.org/wiki/Q7754","display_name":"Mathematical analysis","level":1,"score":0.0},{"id":"https://openalex.org/C120665830","wikidata":"https://www.wikidata.org/wiki/Q14620","display_name":"Optics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/3543622.3578888","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3543622.3578888","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2023 ACM/SIGDA International Symposium on Field Programmable Gate Arrays","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.5099999904632568,"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W1485756991","https://openalex.org/W2376218453","https://openalex.org/W2984236338","https://openalex.org/W1967938402","https://openalex.org/W2386041993","https://openalex.org/W1608572506","https://openalex.org/W2146872326","https://openalex.org/W2518118925","https://openalex.org/W3158825072","https://openalex.org/W3159273459"],"abstract_inverted_index":{"Domain":[0,25,63],"Specific":[1,26,64],"Architectures":[2],"(DSA)":[3],"typically":[4],"apply":[5,202],"heterogeneous":[6,75,195],"compute":[7,76,196],"elements":[8,169,199],"such":[9],"as":[10,200],"FPGAs,":[11],"GPUs,":[12],"AI":[13],"Engines,":[14],"TPUs,":[15],"etc.":[16,42],"towards":[17],"solving":[18],"domain-specific":[19],"problems,":[20],"and":[21,58,94,108,121,146,148,166,170,173,190],"have":[22,29],"their":[23,171],"accompanying":[24],"Software.":[27],"FPGAs":[28,55],"played":[30],"a":[31,50,85],"prominent":[32],"role":[33],"in":[34,56,62],"DSAs":[35,57],"for":[36],"AI,":[37],"Video":[38],"Transcoding,":[39],"Network":[40],"Acceleration":[41],"This":[43],"talk":[44,81,156],"will":[45,82,157,181],"start":[46],"by":[47],"going":[48],"over":[49],"brief":[51],"historical":[52],"survey":[53],"of":[54,88,127,193],"an":[59],"emerging":[60],"trend":[61],"Accelerators,":[65,145],"where":[66],"the":[67,95,110,125,129,136,143,152,159,178,184,187,191,194],"programmable":[68,111],"logic":[69,112],"element":[70,113,189],"is":[71],"paired":[72,115],"with":[73,116,124],"other":[74,117],"or":[77,197],"acceleration":[78,168,198],"elements.":[79],"The":[80,102,155],"then":[83],"perform":[84],"case":[86,103],"study":[87,104],"AMD's":[89],"400G":[90],"Adaptive":[91,147],"SmartNIC/DPU":[92,204],"SoC":[93],"considerations":[96],"that":[97,100],"went":[98],"into":[99],"DSA.":[101],"includes":[105],"where,":[106],"why,":[107],"how":[109],"was":[114],"hardened":[118],"offload":[119,205],"accelerators":[120],"embedded":[122,137],"processors":[123],"goal":[126],"striking":[128],"right":[130],"balance":[131],"between":[132,162,186],"Software":[133],"Processing":[134],"on":[135,142,151,183],"cores,":[138],"Fastpath":[139],"ASIC-like":[140],"processing":[141,150],"Hardened":[144],"Composable":[149],"integrated":[153],"FPGA.":[154],"describe":[158],"data":[160],"movement":[161],"various":[163],"network,":[164],"storage":[165],"interface":[167],"shared":[172],"private":[174],"memory":[175],"resources.":[176],"Throughout":[177],"talk,":[179],"we":[180],"focus":[182],"tradeoffs":[185],"FPGA":[188],"rest":[192],"they":[201],"to":[203],"acceleration.":[206]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2024,"cited_by_count":1},{"year":2023,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}