{"id":"https://openalex.org/W4284964196","doi":"https://doi.org/10.1145/3543544","title":"Design and Implementation of a Coarse-grained Dynamically Reconfigurable Multimedia Accelerator","display_name":"Design and Implementation of a Coarse-grained Dynamically Reconfigurable Multimedia Accelerator","publication_year":2022,"publication_date":"2022-07-09","ids":{"openalex":"https://openalex.org/W4284964196","doi":"https://doi.org/10.1145/3543544"},"language":"en","primary_location":{"id":"doi:10.1145/3543544","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3543544","pdf_url":null,"source":{"id":"https://openalex.org/S2483380313","display_name":"ACM Transactions on Parallel Computing","issn_l":"2329-4949","issn":["2329-4949","2329-4957"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319798","host_organization_name":"Association for Computing Machinery","host_organization_lineage":["https://openalex.org/P4310319798"],"host_organization_lineage_names":["Association for Computing Machinery"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"ACM Transactions on Parallel Computing","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5043490389","display_name":"Hung K. Nguyen","orcid":"https://orcid.org/0000-0003-3417-3447"},"institutions":[{"id":"https://openalex.org/I177233841","display_name":"Vietnam National University, Hanoi","ror":"https://ror.org/02jmfj006","country_code":"VN","type":"education","lineage":["https://openalex.org/I177233841"]}],"countries":["VN"],"is_corresponding":true,"raw_author_name":"Hung K. Nguyen","raw_affiliation_strings":["VNU University of Engineering and Technology, Vietnam National University, Hanoi, Vietnam"],"raw_orcid":"https://orcid.org/0000-0003-3417-3447","affiliations":[{"raw_affiliation_string":"VNU University of Engineering and Technology, Vietnam National University, Hanoi, Vietnam","institution_ids":["https://openalex.org/I177233841"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5022587617","display_name":"Xuan\u2010Tu Tran","orcid":"https://orcid.org/0000-0003-4259-9579"},"institutions":[{"id":"https://openalex.org/I177233841","display_name":"Vietnam National University, Hanoi","ror":"https://ror.org/02jmfj006","country_code":"VN","type":"education","lineage":["https://openalex.org/I177233841"]}],"countries":["VN"],"is_corresponding":false,"raw_author_name":"Xuan-Tu Tran","raw_affiliation_strings":["VNU The Information Technology Institute (ITI), Vietnam National University, Hanoi, Vietnam"],"raw_orcid":"https://orcid.org/0000-0003-4259-9579","affiliations":[{"raw_affiliation_string":"VNU The Information Technology Institute (ITI), Vietnam National University, Hanoi, Vietnam","institution_ids":["https://openalex.org/I177233841"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5043490389"],"corresponding_institution_ids":["https://openalex.org/I177233841"],"apc_list":null,"apc_paid":null,"fwci":0.2331,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.49183857,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":98},"biblio":{"volume":"9","issue":"3","first_page":"1","last_page":"23"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8850241899490356},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.6598273515701294},{"id":"https://openalex.org/keywords/exploit","display_name":"Exploit","score":0.5173603892326355},{"id":"https://openalex.org/keywords/memory-bandwidth","display_name":"Memory bandwidth","score":0.48331379890441895},{"id":"https://openalex.org/keywords/vhdl","display_name":"VHDL","score":0.4645307660102844},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.4525068700313568},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.451865017414093},{"id":"https://openalex.org/keywords/kernel","display_name":"Kernel (algebra)","score":0.4381181001663208},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.43021583557128906},{"id":"https://openalex.org/keywords/memory-hierarchy","display_name":"Memory hierarchy","score":0.42394939064979553},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3519596755504608},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.23657065629959106}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8850241899490356},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.6598273515701294},{"id":"https://openalex.org/C165696696","wikidata":"https://www.wikidata.org/wiki/Q11287","display_name":"Exploit","level":2,"score":0.5173603892326355},{"id":"https://openalex.org/C188045654","wikidata":"https://www.wikidata.org/wiki/Q17148339","display_name":"Memory bandwidth","level":2,"score":0.48331379890441895},{"id":"https://openalex.org/C36941000","wikidata":"https://www.wikidata.org/wiki/Q209455","display_name":"VHDL","level":3,"score":0.4645307660102844},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4525068700313568},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.451865017414093},{"id":"https://openalex.org/C74193536","wikidata":"https://www.wikidata.org/wiki/Q574844","display_name":"Kernel (algebra)","level":2,"score":0.4381181001663208},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.43021583557128906},{"id":"https://openalex.org/C2778100165","wikidata":"https://www.wikidata.org/wiki/Q1589327","display_name":"Memory hierarchy","level":3,"score":0.42394939064979553},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3519596755504608},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.23657065629959106},{"id":"https://openalex.org/C114614502","wikidata":"https://www.wikidata.org/wiki/Q76592","display_name":"Combinatorics","level":1,"score":0.0},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C38652104","wikidata":"https://www.wikidata.org/wiki/Q3510521","display_name":"Computer security","level":1,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/3543544","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3543544","pdf_url":null,"source":{"id":"https://openalex.org/S2483380313","display_name":"ACM Transactions on Parallel Computing","issn_l":"2329-4949","issn":["2329-4949","2329-4957"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319798","host_organization_name":"Association for Computing Machinery","host_organization_lineage":["https://openalex.org/P4310319798"],"host_organization_lineage_names":["Association for Computing Machinery"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"ACM Transactions on Parallel Computing","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":30,"referenced_works":["https://openalex.org/W105298322","https://openalex.org/W1548045585","https://openalex.org/W1577966863","https://openalex.org/W1624904486","https://openalex.org/W2011777138","https://openalex.org/W2025787141","https://openalex.org/W2059628517","https://openalex.org/W2089984858","https://openalex.org/W2090068045","https://openalex.org/W2096589080","https://openalex.org/W2103560185","https://openalex.org/W2117883845","https://openalex.org/W2122171990","https://openalex.org/W2122620713","https://openalex.org/W2122860281","https://openalex.org/W2128145051","https://openalex.org/W2139077369","https://openalex.org/W2167672866","https://openalex.org/W2248705409","https://openalex.org/W2493328864","https://openalex.org/W2626211758","https://openalex.org/W2770380702","https://openalex.org/W2792626659","https://openalex.org/W2970545431","https://openalex.org/W2980612421","https://openalex.org/W3015998244","https://openalex.org/W3036287242","https://openalex.org/W3185974615","https://openalex.org/W4238913942","https://openalex.org/W4241238426"],"related_works":["https://openalex.org/W3004362061","https://openalex.org/W2364622490","https://openalex.org/W2042515040","https://openalex.org/W2383986884","https://openalex.org/W2356141508","https://openalex.org/W4297665406","https://openalex.org/W2749962643","https://openalex.org/W2390807153","https://openalex.org/W2735130281","https://openalex.org/W1990309876"],"abstract_inverted_index":{"This":[0],"article":[1],"proposes":[2],"and":[3,68,131,162,167,194],"implements":[4],"a":[5,49,114,174],"Coarse-grained":[6],"dynamically":[7],"Reconfigurable":[8,11],"Architecture,":[9],"named":[10],"Multimedia":[12],"Accelerator":[13],"(REMAC).":[14],"REMAC":[15,85,157],"architecture":[16,38,86,116,143,166],"is":[17,87,123,171,187],"driven":[18],"by":[19,59,81],"the":[20,30,56,60,64,77,92,97,107,160,165],"pipelined":[21,110],"multi-instruction-multi-data":[22],"execution":[23],"model":[24],"for":[25,136,173],"exploiting":[26],"multi-level":[27],"parallelism":[28],"of":[29,39,48,63,109,117,139,164,177],"computation-intensive":[31],"loops":[32,99],"in":[33,55,96],"multimedia":[34,178],"applications.":[35,179],"The":[36,141,180],"novel":[37,115],"REMAC's":[40,185],"reconfigurable":[41],"processing":[42,83],"unit":[43],"(RPU)":[44],"allows":[45],"multiple":[46],"iterations":[47,130],"kernel":[50,98],"loop":[51],"can":[52],"execute":[53],"concurrently":[54],"pipelining":[57],"fashion":[58],"temporal":[61],"overlapping":[62],"configuration":[65],"fetch,":[66],"execution,":[67],"store":[69],"processes":[70],"as":[71,73],"much":[72],"possible.":[74],"To":[75],"address":[76],"huge":[78],"bandwidth":[79,104],"required":[80],"parallel":[82,137],"units,":[84],"proposed":[88,124,142],"to":[89,100,125,158],"efficiently":[90],"exploit":[91],"abundant":[93],"data":[94,102,120,127,133],"locality":[95],"decrease":[101],"access":[103],"while":[105],"increase":[106,126],"efficiency":[108],"execution.":[111],"In":[112],"addition,":[113],"dedicated":[118],"hierarchy":[119],"memory":[121],"system":[122],"reuse":[128],"between":[129],"make":[132],"always":[134],"available":[135],"operation":[138],"RPU.":[140],"was":[144],"modeled":[145],"at":[146],"RTL":[147],"using":[148],"VHDL":[149],"language.":[150],"Several":[151],"benchmark":[152],"applications":[153],"were":[154],"mapped":[155],"onto":[156],"validate":[159],"high-flexibility":[161],"high-performance":[163],"prove":[168],"that":[169,184],"it":[170],"appropriate":[172],"wide":[175],"set":[176],"experimental":[181],"results":[182],"show":[183],"performance":[186],"better":[188],"than":[189],"Xilinx":[190],"Virtex-II,":[191],"ADRES,":[192],"REMUS-II,":[193],"TI":[195],"C64+":[196],"DSP.":[197]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2023,"cited_by_count":1}],"updated_date":"2026-05-21T06:26:12.895304","created_date":"2025-10-10T00:00:00"}
