{"id":"https://openalex.org/W4293083971","doi":"https://doi.org/10.1145/3543175","title":"CoVerPlan: A <u>Co</u> mprehensive <u>Ver</u> ification <u>Plan</u> ning Framework Leveraging PSS Specifications","display_name":"CoVerPlan: A <u>Co</u> mprehensive <u>Ver</u> ification <u>Plan</u> ning Framework Leveraging PSS Specifications","publication_year":2022,"publication_date":"2022-06-11","ids":{"openalex":"https://openalex.org/W4293083971","doi":"https://doi.org/10.1145/3543175"},"language":"en","primary_location":{"id":"doi:10.1145/3543175","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3543175","pdf_url":null,"source":{"id":"https://openalex.org/S105046310","display_name":"ACM Transactions on Design Automation of Electronic Systems","issn_l":"1084-4309","issn":["1084-4309","1557-7309"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319798","host_organization_name":"Association for Computing Machinery","host_organization_lineage":["https://openalex.org/P4310319798"],"host_organization_lineage_names":["Association for Computing Machinery"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"ACM Transactions on Design Automation of Electronic Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5000985364","display_name":"Sourav Das","orcid":"https://orcid.org/0000-0001-9514-141X"},"institutions":[{"id":"https://openalex.org/I145894827","display_name":"Indian Institute of Technology Kharagpur","ror":"https://ror.org/03w5sq511","country_code":"IN","type":"education","lineage":["https://openalex.org/I145894827"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Sourav Das","raw_affiliation_strings":["Indian Institute of Technology Kharagpur, India"],"raw_orcid":"https://orcid.org/0000-0001-9514-141X","affiliations":[{"raw_affiliation_string":"Indian Institute of Technology Kharagpur, India","institution_ids":["https://openalex.org/I145894827"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5080012092","display_name":"S. Sanyal","orcid":"https://orcid.org/0000-0002-6652-9113"},"institutions":[{"id":"https://openalex.org/I145894827","display_name":"Indian Institute of Technology Kharagpur","ror":"https://ror.org/03w5sq511","country_code":"IN","type":"education","lineage":["https://openalex.org/I145894827"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Sayandeep Sanyal","raw_affiliation_strings":["Indian Institute of Technology Kharagpur, India"],"raw_orcid":"https://orcid.org/0000-0002-6652-9113","affiliations":[{"raw_affiliation_string":"Indian Institute of Technology Kharagpur, India","institution_ids":["https://openalex.org/I145894827"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5022880201","display_name":"Aritra Hazra","orcid":"https://orcid.org/0000-0003-2076-3577"},"institutions":[{"id":"https://openalex.org/I145894827","display_name":"Indian Institute of Technology Kharagpur","ror":"https://ror.org/03w5sq511","country_code":"IN","type":"education","lineage":["https://openalex.org/I145894827"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Aritra Hazra","raw_affiliation_strings":["Indian Institute of Technology Kharagpur, India"],"raw_orcid":"https://orcid.org/0000-0003-2076-3577","affiliations":[{"raw_affiliation_string":"Indian Institute of Technology Kharagpur, India","institution_ids":["https://openalex.org/I145894827"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5033329960","display_name":"Pallab Dasgupta","orcid":"https://orcid.org/0000-0002-2178-8154"},"institutions":[{"id":"https://openalex.org/I145894827","display_name":"Indian Institute of Technology Kharagpur","ror":"https://ror.org/03w5sq511","country_code":"IN","type":"education","lineage":["https://openalex.org/I145894827"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Pallab Dasgupta","raw_affiliation_strings":["Indian Institute of Technology Kharagpur, India"],"raw_orcid":"https://orcid.org/0000-0002-2178-8154","affiliations":[{"raw_affiliation_string":"Indian Institute of Technology Kharagpur, India","institution_ids":["https://openalex.org/I145894827"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.1521,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.50244508,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":"28","issue":"1","first_page":"1","last_page":"32"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10142","display_name":"Formal Methods in Verification","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10142","display_name":"Formal Methods in Verification","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8924285769462585},{"id":"https://openalex.org/keywords/cache-coherence","display_name":"Cache coherence","score":0.5154655575752258},{"id":"https://openalex.org/keywords/functional-verification","display_name":"Functional verification","score":0.49475210905075073},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4789346158504486},{"id":"https://openalex.org/keywords/formal-verification","display_name":"Formal verification","score":0.45438703894615173},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4446050524711609},{"id":"https://openalex.org/keywords/design-flow","display_name":"Design flow","score":0.4237363040447235},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.4127945899963379},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.38770416378974915},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.22990375757217407},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.20247599482536316},{"id":"https://openalex.org/keywords/cpu-cache","display_name":"CPU cache","score":0.1792793869972229}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8924285769462585},{"id":"https://openalex.org/C141917322","wikidata":"https://www.wikidata.org/wiki/Q1025017","display_name":"Cache coherence","level":5,"score":0.5154655575752258},{"id":"https://openalex.org/C62460635","wikidata":"https://www.wikidata.org/wiki/Q5508853","display_name":"Functional verification","level":3,"score":0.49475210905075073},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4789346158504486},{"id":"https://openalex.org/C111498074","wikidata":"https://www.wikidata.org/wiki/Q173326","display_name":"Formal verification","level":2,"score":0.45438703894615173},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4446050524711609},{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.4237363040447235},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.4127945899963379},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.38770416378974915},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.22990375757217407},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.20247599482536316},{"id":"https://openalex.org/C189783530","wikidata":"https://www.wikidata.org/wiki/Q352090","display_name":"CPU cache","level":3,"score":0.1792793869972229},{"id":"https://openalex.org/C38556500","wikidata":"https://www.wikidata.org/wiki/Q13404475","display_name":"Cache algorithms","level":4,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/3543175","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3543175","pdf_url":null,"source":{"id":"https://openalex.org/S105046310","display_name":"ACM Transactions on Design Automation of Electronic Systems","issn_l":"1084-4309","issn":["1084-4309","1557-7309"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319798","host_organization_name":"Association for Computing Machinery","host_organization_lineage":["https://openalex.org/P4310319798"],"host_organization_lineage_names":["Association for Computing Machinery"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"ACM Transactions on Design Automation of Electronic Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.6399999856948853,"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":12,"referenced_works":["https://openalex.org/W1510368738","https://openalex.org/W1819209966","https://openalex.org/W1984559585","https://openalex.org/W2415170901","https://openalex.org/W2417863416","https://openalex.org/W2622925720","https://openalex.org/W2623293810","https://openalex.org/W2764135137","https://openalex.org/W2953793069","https://openalex.org/W3088828811","https://openalex.org/W4240658294","https://openalex.org/W4255744499"],"related_works":["https://openalex.org/W2105593427","https://openalex.org/W3120172095","https://openalex.org/W2118572231","https://openalex.org/W2106507440","https://openalex.org/W2108860137","https://openalex.org/W3209085687","https://openalex.org/W2125238773","https://openalex.org/W2153955347","https://openalex.org/W2533078207","https://openalex.org/W2112298791"],"abstract_inverted_index":{"With":[0],"increasing":[1],"design":[2],"complexity,":[3],"the":[4,78,101,106,125,130,141],"portability":[5],"of":[6,50,62,80,124,132],"tests":[7],"across":[8,59],"different":[9],"designs":[10],"and":[11,24,39,52,109,115,157],"platforms":[12],"becomes":[13],"a":[14,47,71,94,150,158],"key":[15],"criterion":[16],"for":[17,36],"accelerating":[18],"verification":[19,38,73,91,103,123],"closure.":[20],"The":[21,89],"Portable":[22],"Test":[23],"Stimulus":[25],"Standard":[26],"(PSS)":[27],"is":[28],"an":[29],"emerging":[30],"industry":[31],"standard":[32],"prepared":[33],"by":[34,56],"Accellera":[35],"system-on-chip":[37],"testing.":[40],"It":[41],"provides":[42],"language":[43],"constructs":[44],"to":[45,76,99],"create":[46],"target-agnostic":[48],"representation":[49],"stimulus":[51],"test":[53,84],"scenarios":[54],"reused":[55],"various":[57],"users":[58],"many":[60],"levels":[61],"integration.":[63],"In":[64],"this":[65],"article,":[66],"we":[67],"present":[68],"CoVerPlan":[69,118],",":[70],"comprehensive":[72],"framework":[74,92,135],"built":[75],"explore":[77],"power":[79],"action":[81],"inferencing":[82],"on":[83],"models":[85],"written":[86],"in":[87],"PSS.":[88],"proposed":[90,134],"leverages":[93],"Boolean":[95],"satisfiability":[96],"problem":[97],"planner":[98],"unwind":[100],"actual":[102],"flow":[104],"from":[105],"PSS":[107],"specifications":[108],"automatically":[110],"synthesizes":[111],"target-specific":[112],"constraint-random":[113],"testbenches":[114],"formal":[116],"assertions.":[117],"also":[119],"carries":[120],"out":[121],"assertion-based":[122],"synthesized":[126],"properties.":[127],"We":[128],"demonstrate":[129],"efficacy":[131],"our":[133],"over":[136],"several":[137],"case":[138],"studies,":[139],"like":[140],"Advanced":[142],"Microcontroller":[143],"Bus":[144],"Architecture":[145],"advanced":[146],"peripheral":[147],"bus":[148],"protocol,":[149],"simple":[151],"Reduced":[152],"Instruction":[153],"Set":[154],"Computer":[155],"processor,":[156],"cache":[159],"coherence":[160],"protocol.":[161]},"counts_by_year":[{"year":2024,"cited_by_count":1}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}