{"id":"https://openalex.org/W4285676457","doi":"https://doi.org/10.1145/3531437.3539707","title":"A Study on Optimizing Pin Accessibility of Standard Cells in the Post-3 nm Node","display_name":"A Study on Optimizing Pin Accessibility of Standard Cells in the Post-3 nm Node","publication_year":2022,"publication_date":"2022-07-16","ids":{"openalex":"https://openalex.org/W4285676457","doi":"https://doi.org/10.1145/3531437.3539707"},"language":"en","primary_location":{"id":"doi:10.1145/3531437.3539707","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3531437.3539707","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5040857221","display_name":"Jae Hoon Jeong","orcid":"https://orcid.org/0000-0001-8960-6954"},"institutions":[{"id":"https://openalex.org/I31419693","display_name":"Kyungpook National University","ror":"https://ror.org/040c17130","country_code":"KR","type":"education","lineage":["https://openalex.org/I31419693"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Jaehoon Jeong","raw_affiliation_strings":["Kyungpook national university, Republic of Korea"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Kyungpook national university, Republic of Korea","institution_ids":["https://openalex.org/I31419693"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5034027990","display_name":"Jonghyun Ko","orcid":"https://orcid.org/0000-0001-7763-7921"},"institutions":[{"id":"https://openalex.org/I31419693","display_name":"Kyungpook National University","ror":"https://ror.org/040c17130","country_code":"KR","type":"education","lineage":["https://openalex.org/I31419693"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Jonghyun Ko","raw_affiliation_strings":["Kyungpook National University, Republic of Korea"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Kyungpook National University, Republic of Korea","institution_ids":["https://openalex.org/I31419693"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5032455044","display_name":"Taigon Song","orcid":"https://orcid.org/0000-0001-5243-4132"},"institutions":[{"id":"https://openalex.org/I31419693","display_name":"Kyungpook National University","ror":"https://ror.org/040c17130","country_code":"KR","type":"education","lineage":["https://openalex.org/I31419693"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Taigon Song","raw_affiliation_strings":["Kyungpook National University, Republic of Korea"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Kyungpook National University, Republic of Korea","institution_ids":["https://openalex.org/I31419693"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I31419693"],"apc_list":null,"apc_paid":null,"fwci":1.2391,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.74172945,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.702613353729248},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6785861849784851},{"id":"https://openalex.org/keywords/power-consumption","display_name":"Power consumption","score":0.6345161199569702},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.6296247243881226},{"id":"https://openalex.org/keywords/node","display_name":"Node (physics)","score":0.5613909363746643},{"id":"https://openalex.org/keywords/standard-cell","display_name":"Standard cell","score":0.5035483241081238},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.4505954682826996},{"id":"https://openalex.org/keywords/trench","display_name":"Trench","score":0.4393235445022583},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.39893341064453125},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.35982996225357056},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.3595358729362488},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.20303326845169067},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.17783218622207642},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.14778777956962585},{"id":"https://openalex.org/keywords/materials-science","display_name":"Materials science","score":0.09272503852844238}],"concepts":[{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.702613353729248},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6785861849784851},{"id":"https://openalex.org/C2984118289","wikidata":"https://www.wikidata.org/wiki/Q29954","display_name":"Power consumption","level":3,"score":0.6345161199569702},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.6296247243881226},{"id":"https://openalex.org/C62611344","wikidata":"https://www.wikidata.org/wiki/Q1062658","display_name":"Node (physics)","level":2,"score":0.5613909363746643},{"id":"https://openalex.org/C78401558","wikidata":"https://www.wikidata.org/wiki/Q464496","display_name":"Standard cell","level":3,"score":0.5035483241081238},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.4505954682826996},{"id":"https://openalex.org/C155310634","wikidata":"https://www.wikidata.org/wiki/Q1852785","display_name":"Trench","level":3,"score":0.4393235445022583},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.39893341064453125},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.35982996225357056},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.3595358729362488},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.20303326845169067},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.17783218622207642},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.14778777956962585},{"id":"https://openalex.org/C192562407","wikidata":"https://www.wikidata.org/wiki/Q228736","display_name":"Materials science","level":0,"score":0.09272503852844238},{"id":"https://openalex.org/C66938386","wikidata":"https://www.wikidata.org/wiki/Q633538","display_name":"Structural engineering","level":1,"score":0.0},{"id":"https://openalex.org/C159985019","wikidata":"https://www.wikidata.org/wiki/Q181790","display_name":"Composite material","level":1,"score":0.0},{"id":"https://openalex.org/C2779227376","wikidata":"https://www.wikidata.org/wiki/Q6505497","display_name":"Layer (electronics)","level":2,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/3531437.3539707","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3531437.3539707","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Decent work and economic growth","score":0.4000000059604645,"id":"https://metadata.un.org/sdg/8"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":13,"referenced_works":["https://openalex.org/W2007038177","https://openalex.org/W2092902147","https://openalex.org/W2142968870","https://openalex.org/W2346205343","https://openalex.org/W2736534249","https://openalex.org/W2744406216","https://openalex.org/W2772390328","https://openalex.org/W2913404074","https://openalex.org/W2946427270","https://openalex.org/W2973557761","https://openalex.org/W3157234868","https://openalex.org/W3163595402","https://openalex.org/W4234740743"],"related_works":["https://openalex.org/W2103645363","https://openalex.org/W2072989701","https://openalex.org/W3090875125","https://openalex.org/W4205718258","https://openalex.org/W1989674257","https://openalex.org/W2059364457","https://openalex.org/W1738647919","https://openalex.org/W2143608234","https://openalex.org/W3000179092","https://openalex.org/W2050511294"],"abstract_inverted_index":{"Nanosheet":[0],"FETs":[1],"(NSFETs)":[2],"are":[3],"expected":[4],"to":[5,75,141,148],"be":[6,142,149],"the":[7,11,21,29,34,48,77,95,130],"post-FinFET":[8],"device":[9],"in":[10,33,83,86,102,137,151],"technology":[12,139],"nodes":[13,140],"of":[14,24,31,45,97],"5":[15],"nm":[16,153],"and":[17,55,63,93,117,122,144,154],"beyond.":[18,155],"However,":[19],"despite":[20],"high":[22],"potential":[23],"NSFETs,":[25],"few":[26],"studies":[27],"report":[28],"impact":[30],"NSFETs":[32,46],"digital":[35],"VLSI\u2019s":[36],"perspective.":[37],"In":[38],"this":[39,68],"paper,":[40],"we":[41,70,107,128],"present":[42,71],"a":[43],"study":[44],"for":[47,59],"optimal":[49],"standard":[50],"cell":[51],"(SDC)":[52],"library":[53],"design":[54,109],"pin":[56,78],"accessibility-aware":[57],"layout":[58],"less":[60],"routing":[61,88,131],"congestion":[62,132],"low":[64],"power":[65,113],"consumption.":[66],"For":[67],"objective,":[69],"five":[72],"novel":[73],"methodologies":[74],"tackle":[76],"accessibility":[79],"issues":[80,133],"that":[81,134],"rise":[82],"SDC":[84],"designs":[85,147],"extremely-low":[87],"resource":[89],"environments":[90],"(4":[91],"tracks)":[92],"emphasize":[94],"importance":[96],"local":[98],"trench":[99],"contact":[100],"(LTC)":[101],"it.":[103],"Using":[104],"our":[105,126],"methodology,":[106],"improve":[108],"metrics":[110],"such":[111],"as":[112],"consumption,":[114],"total":[115],"area,":[116],"wirelength":[118],"by":[119],"-11.0%,":[120],"-13.2%,":[121],"16.0%,":[123],"respectively.":[124],"By":[125],"study,":[127],"expect":[129],"additionally":[135],"occur":[136],"advanced":[138],"handled":[143],"better":[145],"full-chip":[146],"done":[150],"3":[152]},"counts_by_year":[{"year":2024,"cited_by_count":2},{"year":2023,"cited_by_count":1}],"updated_date":"2026-07-30T17:31:21.811387","created_date":"2025-10-10T00:00:00"}