{"id":"https://openalex.org/W4280644920","doi":"https://doi.org/10.1145/3530390.3532736","title":"Understanding wafer-scale GPU performance using an architectural simulator","display_name":"Understanding wafer-scale GPU performance using an architectural simulator","publication_year":2022,"publication_date":"2022-04-03","ids":{"openalex":"https://openalex.org/W4280644920","doi":"https://doi.org/10.1145/3530390.3532736"},"language":"en","primary_location":{"id":"doi:10.1145/3530390.3532736","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3530390.3532736","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 14th Workshop on General Purpose Processing Using GPU","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5037931597","display_name":"Chris Thames","orcid":"https://orcid.org/0000-0003-2914-6241"},"institutions":[{"id":"https://openalex.org/I16285277","display_name":"William & Mary","ror":"https://ror.org/03hsf0573","country_code":"US","type":"education","lineage":["https://openalex.org/I16285277"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Chris Thames","raw_affiliation_strings":["William and Mary"],"raw_orcid":"https://orcid.org/0000-0003-2914-6241","affiliations":[{"raw_affiliation_string":"William and Mary","institution_ids":["https://openalex.org/I16285277"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5068360756","display_name":"Hang Yan","orcid":"https://orcid.org/0000-0002-3386-8784"},"institutions":[{"id":"https://openalex.org/I47720641","display_name":"Huazhong University of Science and Technology","ror":"https://ror.org/00p991c53","country_code":"CN","type":"education","lineage":["https://openalex.org/I47720641"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Hang Yan","raw_affiliation_strings":["Huazhong University of Science and Technology, Wuhan, Hubei, China"],"raw_orcid":"https://orcid.org/0000-0002-3386-8784","affiliations":[{"raw_affiliation_string":"Huazhong University of Science and Technology, Wuhan, Hubei, China","institution_ids":["https://openalex.org/I47720641"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5041025969","display_name":"Yifan Sun","orcid":"https://orcid.org/0000-0003-3532-6521"},"institutions":[{"id":"https://openalex.org/I16285277","display_name":"William & Mary","ror":"https://ror.org/03hsf0573","country_code":"US","type":"education","lineage":["https://openalex.org/I16285277"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Yifan Sun","raw_affiliation_strings":["William and Mary"],"raw_orcid":"https://orcid.org/0000-0003-3532-6521","affiliations":[{"raw_affiliation_string":"William and Mary","institution_ids":["https://openalex.org/I16285277"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5037931597"],"corresponding_institution_ids":["https://openalex.org/I16285277"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.05365153,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"2"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9983999729156494,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/scalability","display_name":"Scalability","score":0.7917627692222595},{"id":"https://openalex.org/keywords/wafer","display_name":"Wafer","score":0.7430081367492676},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7207770347595215},{"id":"https://openalex.org/keywords/scale","display_name":"Scale (ratio)","score":0.5771933197975159},{"id":"https://openalex.org/keywords/wafer-scale-integration","display_name":"Wafer-scale integration","score":0.415797621011734},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.40673404932022095},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4063580632209778},{"id":"https://openalex.org/keywords/simulation","display_name":"Simulation","score":0.3325800597667694},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.2741384506225586},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.14627021551132202},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.12511366605758667},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.07142090797424316}],"concepts":[{"id":"https://openalex.org/C48044578","wikidata":"https://www.wikidata.org/wiki/Q727490","display_name":"Scalability","level":2,"score":0.7917627692222595},{"id":"https://openalex.org/C160671074","wikidata":"https://www.wikidata.org/wiki/Q267131","display_name":"Wafer","level":2,"score":0.7430081367492676},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7207770347595215},{"id":"https://openalex.org/C2778755073","wikidata":"https://www.wikidata.org/wiki/Q10858537","display_name":"Scale (ratio)","level":2,"score":0.5771933197975159},{"id":"https://openalex.org/C2778638305","wikidata":"https://www.wikidata.org/wiki/Q7406100","display_name":"Wafer-scale integration","level":3,"score":0.415797621011734},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.40673404932022095},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4063580632209778},{"id":"https://openalex.org/C44154836","wikidata":"https://www.wikidata.org/wiki/Q45045","display_name":"Simulation","level":1,"score":0.3325800597667694},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.2741384506225586},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.14627021551132202},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.12511366605758667},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.07142090797424316},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/3530390.3532736","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3530390.3532736","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 14th Workshop on General Purpose Processing Using GPU","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.47999998927116394,"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":4,"referenced_works":["https://openalex.org/W2528784626","https://openalex.org/W2929862812","https://openalex.org/W2952928793","https://openalex.org/W4245911027"],"related_works":["https://openalex.org/W2970498257","https://openalex.org/W2140660040","https://openalex.org/W2041316527","https://openalex.org/W2036313051","https://openalex.org/W4400034431","https://openalex.org/W2065601166","https://openalex.org/W2160598879","https://openalex.org/W2146366317","https://openalex.org/W993605666","https://openalex.org/W2164231539"],"abstract_inverted_index":{"Wafer-Scale":[0],"chips":[1],"have":[2,17],"the":[3,7,19,46,53],"potential":[4],"to":[5,65],"break":[6],"die-size":[8],"limitation":[9],"and":[10,24,48],"provide":[11],"extreme":[12],"performance":[13],"scalability.":[14],"Existing":[15],"solutions":[16],"demonstrated":[18],"possibility":[20],"of":[21,76],"integrating":[22],"multi-CPU":[23],"multi-GPU":[25],"systems":[26],"at":[27],"a":[28,33],"significantly":[29],"larger":[30],"scale":[31],"on":[32,81],"wafer.":[34],"This":[35],"increased":[36],"capability":[37],"results":[38,78],"in":[39,42,44],"an":[40,61,74],"increase":[41],"complexity":[43],"managing":[45],"memory":[47],"computing":[49],"resources.":[50],"To":[51],"support":[52],"community":[54],"studying":[55],"wafer-scale":[56,67,82],"systems,":[57,84],"this":[58,71],"paper":[59],"develops":[60],"architectural":[62],"simulator":[63],"dedicated":[64],"modeling":[66],"multi-device":[68],"systems.":[69],"Also,":[70],"work":[72],"demonstrates":[73],"analysis":[75],"initial":[77],"from":[79],"simulations":[80],"GPU":[83],"providing":[85],"useful":[86],"insight":[87],"that":[88],"can":[89],"guide":[90],"future":[91],"system":[92],"design.":[93]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}