{"id":"https://openalex.org/W4225270023","doi":"https://doi.org/10.1145/3529538.3529562","title":"A source-to-source CUDA to SYCL code migration tool: Intel\u00ae DPC++ Compatibility Tool","display_name":"A source-to-source CUDA to SYCL code migration tool: Intel\u00ae DPC++ Compatibility Tool","publication_year":2022,"publication_date":"2022-05-02","ids":{"openalex":"https://openalex.org/W4225270023","doi":"https://doi.org/10.1145/3529538.3529562"},"language":"en","primary_location":{"id":"doi:10.1145/3529538.3529562","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3529538.3529562","pdf_url":null,"source":{"id":"https://openalex.org/S4306420323","display_name":"International Workshop on OpenCL","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"International Workshop on OpenCL","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5100372803","display_name":"Zhiming Wang","orcid":"https://orcid.org/0000-0002-4933-3303"},"institutions":[],"countries":[],"is_corresponding":true,"raw_author_name":"Zhiming Wang","raw_affiliation_strings":["Intel, China"],"affiliations":[{"raw_affiliation_string":"Intel, China","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5046953991","display_name":"Yury Plyakhin","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Yury Plyakhin","raw_affiliation_strings":["Intel, USA"],"affiliations":[{"raw_affiliation_string":"Intel, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5106416067","display_name":"Chenwei Sun","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Chenwei Sun","raw_affiliation_strings":["Intel, China"],"affiliations":[{"raw_affiliation_string":"Intel, China","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5066940217","display_name":"Ziran Zhang","orcid":"https://orcid.org/0000-0001-7003-2735"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Ziran Zhang","raw_affiliation_strings":["Intel, China"],"affiliations":[{"raw_affiliation_string":"Intel, China","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101741978","display_name":"Zhiwei Jiang","orcid":"https://orcid.org/0000-0001-5104-8811"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Zhiwei Jiang","raw_affiliation_strings":["Intel, China"],"affiliations":[{"raw_affiliation_string":"Intel, China","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5040611179","display_name":"Andy Huang","orcid":"https://orcid.org/0000-0001-8976-2148"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Andy Huang","raw_affiliation_strings":["Intel, China"],"affiliations":[{"raw_affiliation_string":"Intel, China","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5100446064","display_name":"Hao Wang","orcid":"https://orcid.org/0000-0001-9301-5989"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Hao Wang","raw_affiliation_strings":["Intel, China"],"affiliations":[{"raw_affiliation_string":"Intel, China","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":7,"corresponding_author_ids":["https://openalex.org/A5100372803"],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":1.9294,"has_fulltext":false,"cited_by_count":9,"citation_normalized_percentile":{"value":0.85035389,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"2"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9987000226974487,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9987000226974487,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10715","display_name":"Distributed and Parallel Computing Systems","score":0.991599977016449,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":0.9825000166893005,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.813976526260376},{"id":"https://openalex.org/keywords/compiler","display_name":"Compiler","score":0.7625914216041565},{"id":"https://openalex.org/keywords/cuda","display_name":"CUDA","score":0.6964026689529419},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.5383507013320923},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5130430459976196},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.4513475298881531},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.4474676251411438},{"id":"https://openalex.org/keywords/code-generation","display_name":"Code generation","score":0.4359120726585388},{"id":"https://openalex.org/keywords/cross-platform","display_name":"Cross-platform","score":0.4242990016937256},{"id":"https://openalex.org/keywords/source-code","display_name":"Source code","score":0.4109693467617035},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3839521110057831},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3535245358943939}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.813976526260376},{"id":"https://openalex.org/C169590947","wikidata":"https://www.wikidata.org/wiki/Q47506","display_name":"Compiler","level":2,"score":0.7625914216041565},{"id":"https://openalex.org/C2778119891","wikidata":"https://www.wikidata.org/wiki/Q477690","display_name":"CUDA","level":2,"score":0.6964026689529419},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.5383507013320923},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5130430459976196},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.4513475298881531},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.4474676251411438},{"id":"https://openalex.org/C133162039","wikidata":"https://www.wikidata.org/wiki/Q1061077","display_name":"Code generation","level":3,"score":0.4359120726585388},{"id":"https://openalex.org/C92400490","wikidata":"https://www.wikidata.org/wiki/Q174666","display_name":"Cross-platform","level":2,"score":0.4242990016937256},{"id":"https://openalex.org/C43126263","wikidata":"https://www.wikidata.org/wiki/Q128751","display_name":"Source code","level":2,"score":0.4109693467617035},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3839521110057831},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3535245358943939},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0},{"id":"https://openalex.org/C26517878","wikidata":"https://www.wikidata.org/wiki/Q228039","display_name":"Key (lock)","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/3529538.3529562","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3529538.3529562","pdf_url":null,"source":{"id":"https://openalex.org/S4306420323","display_name":"International Workshop on OpenCL","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"International Workshop on OpenCL","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.5899999737739563,"id":"https://metadata.un.org/sdg/10","display_name":"Reduced inequalities"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W650988184","https://openalex.org/W2162410319","https://openalex.org/W2137356287","https://openalex.org/W4321184925","https://openalex.org/W1483618713","https://openalex.org/W60915090","https://openalex.org/W2025840053","https://openalex.org/W2161692994","https://openalex.org/W3122369893","https://openalex.org/W2407476586"],"abstract_inverted_index":{"oneAPI":[0,64,68,117],"[1]":[1],"is":[2,88],"an":[3,7,89],"industry":[4],"initiative":[5],"creating":[6],"open,":[8],"standards-based,":[9],"cross-architecture":[10,38,79],"programming":[11],"model":[12],"to":[13,45,130,134,142,149],"simplify":[14],"development":[15],"for":[16,81,94,99,110,120],"a":[17,24,37,60,95,137,150],"wide":[18],"range":[19],"of":[20,26,63,116],"data-centric":[21],"workloads":[22],"across":[23],"variety":[25],"architectures":[27],"including":[28],"CPU,":[29],"GPU,":[30],"FPGA,":[31],"and":[32,49,54,76,84,118,153],"other":[33],"accelerators.":[34],"It":[35],"includes":[36],"compiler,":[39],"Data":[40],"Parallel":[41],"C++":[42,48],"(DPC++),":[43],"[2]":[44],"support":[46],"ISO":[47],"Khronos":[50,93],"Group's":[51],"SYCL":[52,86,103,163],"[3]":[53,87],"advanced":[55],"libraries.":[56],"Intel":[57,67],"has":[58,162],"created":[59],"product":[61],"implementation":[62],"with":[65],"the":[66,156],"Toolkits.":[69],"These":[70],"help":[71],"developers":[72,128],"efficiently":[73],"build,":[74],"analyze,":[75],"optimize":[77],"high-performance,":[78],"applications":[80,121],"CPUs,":[82],"GPUs,":[83],"FPGAs.":[85],"open":[90],"standard":[91],"from":[92],"portable,":[96],"architecture-neutral":[97],"language":[98,125],"expressing":[100],"parallelism.":[101],"The":[102],"specification":[104],"can":[105,154],"be":[106],"implemented":[107],"by":[108],"anybody":[109],"any":[111,159],"platform.":[112],"To":[113],"take":[114],"advantage":[115],"SYCL,":[119,143],"written":[122],"in":[123],"another":[124],"e.g.,":[126],"CUDA,":[127],"seek":[129],"migrate":[131],"existing":[132],"code":[133,141,157],"SYCL.":[135],"Once":[136],"customer":[138],"migrates":[139],"their":[140],"they":[144],"are":[145],"no":[146],"longer":[147],"tied":[148],"single":[151],"platform":[152,160],"run":[155],"on":[158],"that":[161],"compiler":[164],"support.":[165]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2024,"cited_by_count":3},{"year":2023,"cited_by_count":4},{"year":2022,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}