{"id":"https://openalex.org/W4281804878","doi":"https://doi.org/10.1145/3526241.3530317","title":"An Effective Test Method for Block RAMs in Heterogeneous FPGAs Based on a Novel Partial Bitstream Relocation Technique","display_name":"An Effective Test Method for Block RAMs in Heterogeneous FPGAs Based on a Novel Partial Bitstream Relocation Technique","publication_year":2022,"publication_date":"2022-06-02","ids":{"openalex":"https://openalex.org/W4281804878","doi":"https://doi.org/10.1145/3526241.3530317"},"language":"en","primary_location":{"id":"doi:10.1145/3526241.3530317","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3526241.3530317","pdf_url":null,"source":{"id":"https://openalex.org/S4363608736","display_name":"Proceedings of the Great Lakes Symposium on VLSI 2022","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the Great Lakes Symposium on VLSI 2022","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5030840146","display_name":"Wei Xiong","orcid":"https://orcid.org/0000-0003-2313-3300"},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":true,"raw_author_name":"Wei Xiong","raw_affiliation_strings":["Fudan University, Shanghai, China"],"affiliations":[{"raw_affiliation_string":"Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5102014346","display_name":"Yanze Li","orcid":"https://orcid.org/0000-0003-4647-4482"},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Yanze Li","raw_affiliation_strings":["Fudan University, Shanghai, China"],"affiliations":[{"raw_affiliation_string":"Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5113789250","display_name":"Changpeng Sun","orcid":null},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Changpeng Sun","raw_affiliation_strings":["Fudan University, Shanghai, China"],"affiliations":[{"raw_affiliation_string":"Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5089685937","display_name":"Huanlin Luo","orcid":"https://orcid.org/0000-0002-2802-2725"},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Huanlin Luo","raw_affiliation_strings":["Fudan University, Shanghai, China"],"affiliations":[{"raw_affiliation_string":"Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101726410","display_name":"Jiafeng Liu","orcid":"https://orcid.org/0009-0005-5530-8744"},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Jiafeng Liu","raw_affiliation_strings":["Fudan University, Shanghai, China"],"affiliations":[{"raw_affiliation_string":"Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100370421","display_name":"Jian Wang","orcid":"https://orcid.org/0000-0002-2748-395X"},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Jian Wang","raw_affiliation_strings":["Fudan University, Shanghai, China"],"affiliations":[{"raw_affiliation_string":"Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5081419061","display_name":"Jinmei Lai","orcid":"https://orcid.org/0009-0003-5238-4720"},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Jinmei Lai","raw_affiliation_strings":["Fudan University, Shanghai, China"],"affiliations":[{"raw_affiliation_string":"Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5012474783","display_name":"Gang Qu","orcid":"https://orcid.org/0000-0001-6759-8949"},"institutions":[{"id":"https://openalex.org/I66946132","display_name":"University of Maryland, College Park","ror":"https://ror.org/047s2c258","country_code":"US","type":"education","lineage":["https://openalex.org/I66946132"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Gang Qu","raw_affiliation_strings":["University of Maryland, College Park, College Park, MD, USA"],"affiliations":[{"raw_affiliation_string":"University of Maryland, College Park, College Park, MD, USA","institution_ids":["https://openalex.org/I66946132"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":8,"corresponding_author_ids":["https://openalex.org/A5030840146"],"corresponding_institution_ids":["https://openalex.org/I24943067"],"apc_list":null,"apc_paid":null,"fwci":0.2145,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.28109201,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"275","last_page":"280"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/bitstream","display_name":"Bitstream","score":0.9123060703277588},{"id":"https://openalex.org/keywords/control-reconfiguration","display_name":"Control reconfiguration","score":0.7803725004196167},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7590240240097046},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.708514392375946},{"id":"https://openalex.org/keywords/static-random-access-memory","display_name":"Static random-access memory","score":0.7069862484931946},{"id":"https://openalex.org/keywords/block","display_name":"Block (permutation group theory)","score":0.6373081207275391},{"id":"https://openalex.org/keywords/overhead","display_name":"Overhead (engineering)","score":0.6172837615013123},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5797433853149414},{"id":"https://openalex.org/keywords/fault-coverage","display_name":"Fault coverage","score":0.5090956091880798},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3533848524093628},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3296188712120056},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.29067540168762207},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.2839964032173157},{"id":"https://openalex.org/keywords/decoding-methods","display_name":"Decoding methods","score":0.22433960437774658},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.10885035991668701}],"concepts":[{"id":"https://openalex.org/C136695289","wikidata":"https://www.wikidata.org/wiki/Q415568","display_name":"Bitstream","level":3,"score":0.9123060703277588},{"id":"https://openalex.org/C119701452","wikidata":"https://www.wikidata.org/wiki/Q5165881","display_name":"Control reconfiguration","level":2,"score":0.7803725004196167},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7590240240097046},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.708514392375946},{"id":"https://openalex.org/C68043766","wikidata":"https://www.wikidata.org/wiki/Q267416","display_name":"Static random-access memory","level":2,"score":0.7069862484931946},{"id":"https://openalex.org/C2777210771","wikidata":"https://www.wikidata.org/wiki/Q4927124","display_name":"Block (permutation group theory)","level":2,"score":0.6373081207275391},{"id":"https://openalex.org/C2779960059","wikidata":"https://www.wikidata.org/wiki/Q7113681","display_name":"Overhead (engineering)","level":2,"score":0.6172837615013123},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5797433853149414},{"id":"https://openalex.org/C126953365","wikidata":"https://www.wikidata.org/wiki/Q5438152","display_name":"Fault coverage","level":3,"score":0.5090956091880798},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3533848524093628},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3296188712120056},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.29067540168762207},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.2839964032173157},{"id":"https://openalex.org/C57273362","wikidata":"https://www.wikidata.org/wiki/Q576722","display_name":"Decoding methods","level":2,"score":0.22433960437774658},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.10885035991668701},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/3526241.3530317","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3526241.3530317","pdf_url":null,"source":{"id":"https://openalex.org/S4363608736","display_name":"Proceedings of the Great Lakes Symposium on VLSI 2022","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the Great Lakes Symposium on VLSI 2022","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":11,"referenced_works":["https://openalex.org/W1995794852","https://openalex.org/W2002190968","https://openalex.org/W2022202167","https://openalex.org/W2075397577","https://openalex.org/W2093467715","https://openalex.org/W2159913676","https://openalex.org/W2588101650","https://openalex.org/W2762119053","https://openalex.org/W2797449020","https://openalex.org/W2913355112","https://openalex.org/W4247767635"],"related_works":["https://openalex.org/W2399954712","https://openalex.org/W2901561495","https://openalex.org/W2124601977","https://openalex.org/W2172988812","https://openalex.org/W2093752973","https://openalex.org/W2536416664","https://openalex.org/W2758955467","https://openalex.org/W42103239","https://openalex.org/W2077143820","https://openalex.org/W1637603355"],"abstract_inverted_index":{"Block":[0],"RAMs":[1],"(BRAMs)":[2],"play":[3],"an":[4],"important":[5],"role":[6],"in":[7,44,126,146,154],"modern":[8],"heterogenous":[9],"FPGAs,":[10],"hence":[11],"how":[12],"to":[13,66,84,105,108,172,190,194],"test":[14,71,116,130,174],"them":[15],"comprehensively":[16],"and":[17,101,139,150,166],"effectively":[18],"becomes":[19],"a":[20,120,133,195],"major":[21],"concern.":[22],"On-chip":[23],"Partial":[24,33],"Bitstream":[25],"Relocation":[26],"(PBR)":[27],"technique":[28,63,123],"based":[29,118],"on":[30,41,119],"FPGA":[31,45],"Dynamic":[32],"Reconfiguration":[34],"(DPR)":[35],"can":[36,187],"decrease":[37],"the":[38,48,57,88,141,179,183],"time":[39,197],"spent":[40],"configuring":[42],"modules":[43],"while":[46],"reducing":[47],"memory":[49],"resources":[50],"overhead":[51],"for":[52,79,91,137,144],"storing":[53],"partial":[54],"bitstreams":[55],"of":[56,185],"reconfigurable":[58],"modules.":[59],"The":[60],"previous":[61],"PBR":[62,122,181],"is":[64,94,98,124],"difficult":[65],"be":[67,106,188],"combined":[68],"with":[69,162,178],"BRAM":[70,92,115,138,147,168],"directly,":[72],"because":[73],"they":[74],"are":[75,159,170],"somehow":[76],"tedious,":[77],"unsuitable":[78],"large-scale":[80],"design":[81],"or":[82],"limited":[83],"specific":[85],"devices.":[86],"Besides,":[87],"problem":[89],"exists":[90],"testing":[93,102,142],"that":[95],"fault":[96,111,135],"model":[97,136],"still":[99],"incomplete":[100],"algorithms":[103,143],"need":[104],"improved":[107],"achieve":[109],"higher":[110],"coverage.":[112],"An":[113],"Effective":[114],"method":[117,131],"novel":[121],"proposed":[125,180],"this":[127],"paper.":[128],"Our":[129],"establishes":[132],"complete":[134],"improves":[140],"faults":[145,153],"ECC":[148],"circuits":[149],"intra-word":[151],"coupling":[152],"SRAM":[155],"cells.":[156],"On-board":[157],"experiments":[158],"carried":[160],"out":[161],"Xilinx":[163],"xc7vx690t":[164],"device,":[165],"14":[167],"configurations":[169,186],"used":[171],"fully":[173],"BRAMs.":[175],"In":[176],"conjunction":[177],"technique,":[182],"number":[184],"reduced":[189],"10,":[191],"which":[192],"leads":[193],"35.7%":[196],"saving.":[198]},"counts_by_year":[{"year":2024,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
