{"id":"https://openalex.org/W4312121047","doi":"https://doi.org/10.1145/3508352.3549424","title":"An MLIR-based Compiler Flow for System-Level Design and Hardware Acceleration","display_name":"An MLIR-based Compiler Flow for System-Level Design and Hardware Acceleration","publication_year":2022,"publication_date":"2022-10-30","ids":{"openalex":"https://openalex.org/W4312121047","doi":"https://doi.org/10.1145/3508352.3549424"},"language":"en","primary_location":{"id":"doi:10.1145/3508352.3549424","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3508352.3549424","pdf_url":null,"source":{"id":"https://openalex.org/S4363608844","display_name":"Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"green","oa_url":"https://hdl.handle.net/11311/1229389","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5057498242","display_name":"N\u00edcolas Bohm Agostini","orcid":"https://orcid.org/0000-0003-1855-3810"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Nicolas Bohm Agostini","raw_affiliation_strings":["PNNL"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"PNNL","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5033121816","display_name":"Serena Curzel","orcid":"https://orcid.org/0000-0002-8202-1627"},"institutions":[{"id":"https://openalex.org/I93860229","display_name":"Politecnico di Milano","ror":"https://ror.org/01nffqt88","country_code":"IT","type":"education","lineage":["https://openalex.org/I93860229"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Serena Curzel","raw_affiliation_strings":["Politecnico di Milano, Milan, Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Politecnico di Milano, Milan, Italy","institution_ids":["https://openalex.org/I93860229"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5019702659","display_name":"Vinay Amatya","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Vinay Amatya","raw_affiliation_strings":["PNNL"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"PNNL","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5059973546","display_name":"Cheng Tan","orcid":"https://orcid.org/0000-0003-3727-2889"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Cheng Tan","raw_affiliation_strings":["PNNL"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"PNNL","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5074554647","display_name":"Marco Minutoli","orcid":"https://orcid.org/0000-0002-4220-1420"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Marco Minutoli","raw_affiliation_strings":["PNNL"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"PNNL","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5000893617","display_name":"Vito Giovanni Castellana","orcid":"https://orcid.org/0000-0003-3516-7903"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Vito Giovanni Castellana","raw_affiliation_strings":["PNNL"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"PNNL","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5010169378","display_name":"Joseph Manzano","orcid":"https://orcid.org/0000-0002-6616-0125"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Joseph Manzano","raw_affiliation_strings":["PNNL"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"PNNL","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5061128237","display_name":"David Kaeli","orcid":"https://orcid.org/0000-0002-5692-0151"},"institutions":[{"id":"https://openalex.org/I87182695","display_name":"Universidad del Noreste","ror":"https://ror.org/02ahky613","country_code":"MX","type":"education","lineage":["https://openalex.org/I87182695"]}],"countries":["MX"],"is_corresponding":false,"raw_author_name":"David Kaeli","raw_affiliation_strings":["Northeastern University"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Northeastern University","institution_ids":["https://openalex.org/I87182695"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5041853964","display_name":"Antonino Tumeo","orcid":"https://orcid.org/0000-0001-9452-120X"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Antonino Tumeo","raw_affiliation_strings":["PNNL"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"PNNL","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":9,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":6.3992,"has_fulltext":false,"cited_by_count":34,"citation_normalized_percentile":{"value":0.98493976,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":90,"max":99},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"9"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10036","display_name":"Advanced Neural Network Applications","score":0.9987999796867371,"subfield":{"id":"https://openalex.org/subfields/1707","display_name":"Computer Vision and Pattern Recognition"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9977999925613403,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8881276845932007},{"id":"https://openalex.org/keywords/compiler","display_name":"Compiler","score":0.8724907636642456},{"id":"https://openalex.org/keywords/benchmark","display_name":"Benchmark (surveying)","score":0.6717027425765991},{"id":"https://openalex.org/keywords/granularity","display_name":"Granularity","score":0.5884637832641602},{"id":"https://openalex.org/keywords/speedup","display_name":"Speedup","score":0.549380898475647},{"id":"https://openalex.org/keywords/optimizing-compiler","display_name":"Optimizing compiler","score":0.5201480984687805},{"id":"https://openalex.org/keywords/high-level-synthesis","display_name":"High-level synthesis","score":0.5141806602478027},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.4772096276283264},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.45660120248794556},{"id":"https://openalex.org/keywords/code-generation","display_name":"Code generation","score":0.4450913965702057},{"id":"https://openalex.org/keywords/domain-specific-language","display_name":"Domain-specific language","score":0.4241604208946228},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.3338467478752136},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3322860598564148},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.22409042716026306},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.17603880167007446},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.14910942316055298}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8881276845932007},{"id":"https://openalex.org/C169590947","wikidata":"https://www.wikidata.org/wiki/Q47506","display_name":"Compiler","level":2,"score":0.8724907636642456},{"id":"https://openalex.org/C185798385","wikidata":"https://www.wikidata.org/wiki/Q1161707","display_name":"Benchmark (surveying)","level":2,"score":0.6717027425765991},{"id":"https://openalex.org/C177774035","wikidata":"https://www.wikidata.org/wiki/Q1246948","display_name":"Granularity","level":2,"score":0.5884637832641602},{"id":"https://openalex.org/C68339613","wikidata":"https://www.wikidata.org/wiki/Q1549489","display_name":"Speedup","level":2,"score":0.549380898475647},{"id":"https://openalex.org/C190902152","wikidata":"https://www.wikidata.org/wiki/Q1325106","display_name":"Optimizing compiler","level":3,"score":0.5201480984687805},{"id":"https://openalex.org/C58013763","wikidata":"https://www.wikidata.org/wiki/Q5754574","display_name":"High-level synthesis","level":3,"score":0.5141806602478027},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4772096276283264},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.45660120248794556},{"id":"https://openalex.org/C133162039","wikidata":"https://www.wikidata.org/wiki/Q1061077","display_name":"Code generation","level":3,"score":0.4450913965702057},{"id":"https://openalex.org/C135257023","wikidata":"https://www.wikidata.org/wiki/Q691358","display_name":"Domain-specific language","level":2,"score":0.4241604208946228},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.3338467478752136},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3322860598564148},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.22409042716026306},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.17603880167007446},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.14910942316055298},{"id":"https://openalex.org/C26517878","wikidata":"https://www.wikidata.org/wiki/Q228039","display_name":"Key (lock)","level":2,"score":0.0},{"id":"https://openalex.org/C205649164","wikidata":"https://www.wikidata.org/wiki/Q1071","display_name":"Geography","level":0,"score":0.0},{"id":"https://openalex.org/C13280743","wikidata":"https://www.wikidata.org/wiki/Q131089","display_name":"Geodesy","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1145/3508352.3549424","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3508352.3549424","pdf_url":null,"source":{"id":"https://openalex.org/S4363608844","display_name":"Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design","raw_type":"proceedings-article"},{"id":"pmh:oai:re.public.polimi.it:11311/1229389","is_oa":true,"landing_page_url":"https://hdl.handle.net/11311/1229389","pdf_url":null,"source":{"id":"https://openalex.org/S4306400312","display_name":"Virtual Community of Pathological Anatomy (University of Castilla La Mancha)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I79189158","host_organization_name":"University of Castilla-La Mancha","host_organization_lineage":["https://openalex.org/I79189158"],"host_organization_lineage_names":[],"type":"repository"},"license":"other-oa","license_id":"https://openalex.org/licenses/other-oa","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"info:eu-repo/semantics/conferenceObject"}],"best_oa_location":{"id":"pmh:oai:re.public.polimi.it:11311/1229389","is_oa":true,"landing_page_url":"https://hdl.handle.net/11311/1229389","pdf_url":null,"source":{"id":"https://openalex.org/S4306400312","display_name":"Virtual Community of Pathological Anatomy (University of Castilla La Mancha)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I79189158","host_organization_name":"University of Castilla-La Mancha","host_organization_lineage":["https://openalex.org/I79189158"],"host_organization_lineage_names":[],"type":"repository"},"license":"other-oa","license_id":"https://openalex.org/licenses/other-oa","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"info:eu-repo/semantics/conferenceObject"},"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","score":0.6499999761581421,"id":"https://metadata.un.org/sdg/9"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":24,"referenced_works":["https://openalex.org/W2004250488","https://openalex.org/W2565125333","https://openalex.org/W2783614532","https://openalex.org/W2792801541","https://openalex.org/W2889424113","https://openalex.org/W2890823284","https://openalex.org/W2891899936","https://openalex.org/W2899915146","https://openalex.org/W2906737788","https://openalex.org/W2912406262","https://openalex.org/W3011509423","https://openalex.org/W3091969046","https://openalex.org/W3104395752","https://openalex.org/W3112948415","https://openalex.org/W3121932930","https://openalex.org/W3122286897","https://openalex.org/W3122749996","https://openalex.org/W3144814738","https://openalex.org/W3205717712","https://openalex.org/W3211485653","https://openalex.org/W3212867926","https://openalex.org/W4200591385","https://openalex.org/W4293025825","https://openalex.org/W4293210517"],"related_works":["https://openalex.org/W2794657471","https://openalex.org/W1970499202","https://openalex.org/W818898529","https://openalex.org/W2068555872","https://openalex.org/W4252190617","https://openalex.org/W1963927741","https://openalex.org/W2172096703","https://openalex.org/W4245356976","https://openalex.org/W307712065","https://openalex.org/W2766929565"],"abstract_inverted_index":{"The":[0],"generation":[1,129],"of":[2,100,121,130,167,186,193,203],"custom":[3],"hardware":[4],"accelerators":[5,46,131,169],"for":[6,111,132,177],"applications":[7],"implemented":[8],"within":[9],"high-level":[10,48,54,162],"productive":[11],"programming":[12,55],"frameworks":[13],"requires":[14],"considerable":[15],"manual":[16],"effort.":[17],"To":[18],"automate":[19],"this":[20],"process,":[21],"we":[22],"introduce":[23],"SODA-OPT,":[24],"a":[25,91],"compiler":[26,71,101],"tool":[27],"that":[28,60,106,160,176],"extends":[29],"the":[30,63,98,118,122,127,156,178,184,194],"MLIR":[31,64],"infrastructure.":[32,65],"SODA-OPT":[33,50,69,82,205],"automatically":[34],"searches,":[35],"outlines,":[36],"tiles,":[37],"and":[38,57,104,114,141,196],"pre-optimizes":[39],"relevant":[40],"code":[41],"regions":[42],"to":[43,81,90,96,171],"generate":[44],"high-quality":[45],"through":[47,83],"synthesis.":[49],"can":[51],"support":[52],"any":[53],"framework":[56],"domain-specific":[58],"language":[59],"interface":[61],"with":[62,74,145,153],"By":[66],"leveraging":[67],"MLIR,":[68],"solves":[70],"optimization":[72,102],"problems":[73],"specialized":[75],"abstractions.":[76],"Backend":[77],"synthesis":[78],"tools":[79],"connect":[80],"progressive":[84],"intermediate":[85],"representation":[86],"lowerings.":[87],"SODAOPT":[88],"interfaces":[89],"design":[92],"space":[93],"exploration":[94],"engine":[95],"identify":[97],"combination":[99],"passes":[103],"options":[105],"provides":[107,197],"high-performance":[108],"generated":[109],"designs":[110],"different":[112],"backends":[113],"targets.":[115],"We":[116,173],"demonstrate":[117],"practical":[119],"applicability":[120],"compilation":[123],"flow":[124],"by":[125,142],"exploring":[126],"automatic":[128],"deep":[133],"neural":[134],"networks":[135],"operators":[136],"outlined":[137],"at":[138,212],"arbitrary":[139],"granularity":[140],"combining":[143],"outlining":[144],"tiling":[146],"on":[147],"large":[148],"convolution":[149],"layers.":[150],"Experimental":[151],"results":[152],"kernels":[154],"from":[155],"PolyBench":[157],"benchmark":[158],"show":[159,175],"our":[161,181],"optimizations":[163],"improve":[164],"execution":[165],"delays":[166],"synthesized":[168],"up":[170],"60x.":[172],"also":[174],"selected":[179],"kernels,":[180],"solution":[182],"outperforms":[183],"current":[185],"state-ofthe":[187],"art":[188],"in":[189,201],"more":[190],"than":[191],"70%":[192],"benchmarks":[195],"better":[198],"average":[199],"speedup":[200],"55%":[202],"them.":[204],"is":[206],"an":[207],"open":[208],"source":[209],"project":[210],"available":[211],"https://gitlab.pnnl.gov/sodalite/soda-opt.":[213]},"counts_by_year":[{"year":2026,"cited_by_count":4},{"year":2025,"cited_by_count":10},{"year":2024,"cited_by_count":14},{"year":2023,"cited_by_count":5},{"year":2022,"cited_by_count":1}],"updated_date":"2026-06-19T17:40:00.097472","created_date":"2025-10-10T00:00:00"}