{"id":"https://openalex.org/W4223974038","doi":"https://doi.org/10.1145/3505170.3506731","title":"RTL-MP","display_name":"RTL-MP","publication_year":2022,"publication_date":"2022-04-13","ids":{"openalex":"https://openalex.org/W4223974038","doi":"https://doi.org/10.1145/3505170.3506731"},"language":"en","primary_location":{"id":"doi:10.1145/3505170.3506731","is_oa":true,"landing_page_url":"https://doi.org/10.1145/3505170.3506731","pdf_url":"https://dl.acm.org/doi/pdf/10.1145/3505170.3506731","source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2022 International Symposium on Physical Design","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"gold","oa_url":"https://dl.acm.org/doi/pdf/10.1145/3505170.3506731","any_repository_has_fulltext":null},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5073558386","display_name":"Andrew B. Kahng","orcid":"https://orcid.org/0000-0002-4490-5018"},"institutions":[{"id":"https://openalex.org/I36258959","display_name":"University of California San Diego","ror":"https://ror.org/0168r3w48","country_code":"US","type":"education","lineage":["https://openalex.org/I36258959"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Andrew B. Kahng","raw_affiliation_strings":["University of California, San Diego, La Jolla, CA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of California, San Diego, La Jolla, CA, USA","institution_ids":["https://openalex.org/I36258959"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5111528015","display_name":"Ravi Varadarajan","orcid":null},"institutions":[{"id":"https://openalex.org/I36258959","display_name":"University of California San Diego","ror":"https://ror.org/0168r3w48","country_code":"US","type":"education","lineage":["https://openalex.org/I36258959"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Ravi Varadarajan","raw_affiliation_strings":["University of California, San Diego, La Jolla, CA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of California, San Diego, La Jolla, CA, USA","institution_ids":["https://openalex.org/I36258959"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5078035974","display_name":"Zhiang Wang","orcid":"https://orcid.org/0000-0002-6669-9702"},"institutions":[{"id":"https://openalex.org/I36258959","display_name":"University of California San Diego","ror":"https://ror.org/0168r3w48","country_code":"US","type":"education","lineage":["https://openalex.org/I36258959"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Zhiang Wang","raw_affiliation_strings":["University of California, San Diego, La Jolla, CA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of California, San Diego, La Jolla, CA, USA","institution_ids":["https://openalex.org/I36258959"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I36258959"],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":true,"cited_by_count":20,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"3","last_page":"11"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9983000159263611,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.996999979019165,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/floorplan","display_name":"Floorplan","score":0.8514701128005981},{"id":"https://openalex.org/keywords/dataflow","display_name":"Dataflow","score":0.7893359661102295},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7800440788269043},{"id":"https://openalex.org/keywords/macro","display_name":"Macro","score":0.555172860622406},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5294960141181946},{"id":"https://openalex.org/keywords/physical-design","display_name":"Physical design","score":0.49819183349609375},{"id":"https://openalex.org/keywords/electronic-design-automation","display_name":"Electronic design automation","score":0.44762253761291504},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.4342096447944641},{"id":"https://openalex.org/keywords/quality","display_name":"Quality (philosophy)","score":0.42195233702659607},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3720695376396179},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3396915793418884},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.20138710737228394},{"id":"https://openalex.org/keywords/circuit-design","display_name":"Circuit design","score":0.1893969178199768},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.18692246079444885},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.14965367317199707}],"concepts":[{"id":"https://openalex.org/C130145326","wikidata":"https://www.wikidata.org/wiki/Q1553985","display_name":"Floorplan","level":2,"score":0.8514701128005981},{"id":"https://openalex.org/C96324660","wikidata":"https://www.wikidata.org/wiki/Q205446","display_name":"Dataflow","level":2,"score":0.7893359661102295},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7800440788269043},{"id":"https://openalex.org/C166955791","wikidata":"https://www.wikidata.org/wiki/Q629579","display_name":"Macro","level":2,"score":0.555172860622406},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5294960141181946},{"id":"https://openalex.org/C188817802","wikidata":"https://www.wikidata.org/wiki/Q13426855","display_name":"Physical design","level":3,"score":0.49819183349609375},{"id":"https://openalex.org/C64260653","wikidata":"https://www.wikidata.org/wiki/Q1194864","display_name":"Electronic design automation","level":2,"score":0.44762253761291504},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.4342096447944641},{"id":"https://openalex.org/C2779530757","wikidata":"https://www.wikidata.org/wiki/Q1207505","display_name":"Quality (philosophy)","level":2,"score":0.42195233702659607},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3720695376396179},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3396915793418884},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.20138710737228394},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.1893969178199768},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.18692246079444885},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.14965367317199707},{"id":"https://openalex.org/C111472728","wikidata":"https://www.wikidata.org/wiki/Q9471","display_name":"Epistemology","level":1,"score":0.0},{"id":"https://openalex.org/C138885662","wikidata":"https://www.wikidata.org/wiki/Q5891","display_name":"Philosophy","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/3505170.3506731","is_oa":true,"landing_page_url":"https://doi.org/10.1145/3505170.3506731","pdf_url":"https://dl.acm.org/doi/pdf/10.1145/3505170.3506731","source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2022 International Symposium on Physical Design","raw_type":"proceedings-article"}],"best_oa_location":{"id":"doi:10.1145/3505170.3506731","is_oa":true,"landing_page_url":"https://doi.org/10.1145/3505170.3506731","pdf_url":"https://dl.acm.org/doi/pdf/10.1145/3505170.3506731","source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2022 International Symposium on Physical Design","raw_type":"proceedings-article"},"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure","score":0.6499999761581421}],"awards":[],"funders":[],"has_content":{"grobid_xml":true,"pdf":true},"content_urls":{"pdf":"https://content.openalex.org/works/W4223974038.pdf","grobid_xml":"https://content.openalex.org/works/W4223974038.grobid-xml"},"referenced_works_count":45,"referenced_works":["https://openalex.org/W1644473063","https://openalex.org/W1969091636","https://openalex.org/W1992200860","https://openalex.org/W1993038918","https://openalex.org/W1993509482","https://openalex.org/W1996965221","https://openalex.org/W2002330922","https://openalex.org/W2024060531","https://openalex.org/W2031974129","https://openalex.org/W2055907840","https://openalex.org/W2064910292","https://openalex.org/W2095550547","https://openalex.org/W2097682727","https://openalex.org/W2100740271","https://openalex.org/W2104073053","https://openalex.org/W2109826730","https://openalex.org/W2112190147","https://openalex.org/W2114772983","https://openalex.org/W2118163232","https://openalex.org/W2122425352","https://openalex.org/W2126551091","https://openalex.org/W2129115040","https://openalex.org/W2131979475","https://openalex.org/W2132693178","https://openalex.org/W2141746747","https://openalex.org/W2154462472","https://openalex.org/W2155230244","https://openalex.org/W2293911681","https://openalex.org/W2883265831","https://openalex.org/W2895267889","https://openalex.org/W2909290526","https://openalex.org/W2945284777","https://openalex.org/W2945702761","https://openalex.org/W2997784719","https://openalex.org/W3018195242","https://openalex.org/W3019806800","https://openalex.org/W3111684605","https://openalex.org/W3113752050","https://openalex.org/W3115480774","https://openalex.org/W3131660762","https://openalex.org/W3171752851","https://openalex.org/W4247344326","https://openalex.org/W4256263672","https://openalex.org/W6636418497","https://openalex.org/W6681251239"],"related_works":["https://openalex.org/W2781601456","https://openalex.org/W3010631755","https://openalex.org/W2783276420","https://openalex.org/W2186482337","https://openalex.org/W2115502122","https://openalex.org/W4249576260","https://openalex.org/W2903073708","https://openalex.org/W2138401961","https://openalex.org/W2161355881","https://openalex.org/W2097806352"],"abstract_inverted_index":{"In":[0,65],"a":[1,71,155],"typical":[2],"RTL-\u00adto-\u00adGDSII":[3],"flow,":[4],"floorplanning":[5,58],"plays":[6],"an":[7],"essential":[8],"role":[9],"in":[10,119],"achieving":[11],"decent":[12],"quality":[13],"of":[14,33,45,157,172],"results":[15],"(QoR).":[16],"A":[17],"good":[18],"floorplan":[19],"typically":[20],"requires":[21],"interaction":[22,84],"between":[23,85],"the":[24,31,34,37,57,83,86,91,102,116,120,124],"frontend":[25,87],"designer,":[26],"who":[27],"is":[28],"responsible":[29],"for":[30],"functionality":[32],"RTL,":[35],"and":[36,63,79,90,105,122,151,166],"backend":[38,92],"physical":[39,93],"design":[40,94],"engineer.":[41],"The":[42],"increasing":[43],"complexity":[44],"macro-\u00addominated":[46],"designs":[47],"(especially":[48],"machine":[49],"learning":[50],"accelerators":[51],"with":[52],"autogenerated":[53],"RTL)":[54],"has":[55],"made":[56],"task":[59],"even":[60],"more":[61],"challenging":[62],"time\u00ad-consuming.":[64],"this":[66],"paper,":[67],"we":[68],"propose":[69],"RTL-\u00adMP,":[70],"novel":[72],"macro":[73,129,164],"placer":[74],"which":[75],"utilizes":[76],"RTL":[77,88,121],"information":[78,126],"tries":[80],"to":[81,96,127,135,154,170],"\"mimic\"":[82],"designer":[89],"engineer":[95],"produce":[97],"human-\u00adquality":[98],"floorplans.":[99,174],"By":[100],"exploiting":[101],"logical":[103,107],"hierarchy":[104],"processing":[106],"modules":[108],"based":[109,139,147],"on":[110,140,148],"connection":[111],"signatures,":[112],"RTL-\u00adMP":[113,153],"can":[114],"capture":[115],"dataflow":[117,125],"inherent":[118],"use":[123],"guide":[128],"placement.":[130],"We":[131,143],"also":[132],"apply":[133],"autotuning":[134],"optimize":[136],"hyperparameter":[137],"settings":[138],"input":[141],"designs.":[142,159],"have":[144],"built":[145],"RTL\u00ad-MP":[146,160],"OpenROAD":[149],"infrastructure":[150],"applied":[152],"set":[156],"industrial":[158],"outperforms":[161],"state-\u00adof-\u00adthe\u00ad-art":[162],"commercial":[163],"placers":[165],"achieves":[167],"QoR":[168],"similar":[169],"that":[171],"handcrafted":[173]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2025,"cited_by_count":5},{"year":2024,"cited_by_count":7},{"year":2023,"cited_by_count":4},{"year":2022,"cited_by_count":3}],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2022-04-19T00:00:00"}