{"id":"https://openalex.org/W3217045338","doi":"https://doi.org/10.1145/3491234","title":"Rethinking Embedded Blocks for Machine Learning Applications","display_name":"Rethinking Embedded Blocks for Machine Learning Applications","publication_year":2021,"publication_date":"2021-11-30","ids":{"openalex":"https://openalex.org/W3217045338","doi":"https://doi.org/10.1145/3491234","mag":"3217045338"},"language":"en","primary_location":{"id":"doi:10.1145/3491234","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3491234","pdf_url":null,"source":{"id":"https://openalex.org/S112809824","display_name":"ACM Transactions on Reconfigurable Technology and Systems","issn_l":"1936-7406","issn":["1936-7406","1936-7414"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319798","host_organization_name":"Association for Computing Machinery","host_organization_lineage":["https://openalex.org/P4310319798"],"host_organization_lineage_names":["Association for Computing Machinery"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"ACM Transactions on Reconfigurable Technology and Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5047461191","display_name":"S A Rasoulinezhad","orcid":"https://orcid.org/0000-0002-7366-8533"},"institutions":[{"id":"https://openalex.org/I129604602","display_name":"The University of Sydney","ror":"https://ror.org/0384j8v12","country_code":"AU","type":"education","lineage":["https://openalex.org/I129604602"]}],"countries":["AU"],"is_corresponding":false,"raw_author_name":"Seyedramin Rasoulinezhad","raw_affiliation_strings":["The University of Sydney, NSW, Australia"],"raw_orcid":"https://orcid.org/0000-0002-7366-8533","affiliations":[{"raw_affiliation_string":"The University of Sydney, NSW, Australia","institution_ids":["https://openalex.org/I129604602"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5008588979","display_name":"Esther Roorda","orcid":"https://orcid.org/0000-0002-1905-9577"},"institutions":[{"id":"https://openalex.org/I141945490","display_name":"University of British Columbia","ror":"https://ror.org/03rmrcq20","country_code":"CA","type":"education","lineage":["https://openalex.org/I141945490"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Esther Roorda","raw_affiliation_strings":["The University of British Columbia, Vancouver, BC, Canada"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"The University of British Columbia, Vancouver, BC, Canada","institution_ids":["https://openalex.org/I141945490"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5013246362","display_name":"Steven J. E. Wilton","orcid":"https://orcid.org/0000-0002-1241-6690"},"institutions":[{"id":"https://openalex.org/I141945490","display_name":"University of British Columbia","ror":"https://ror.org/03rmrcq20","country_code":"CA","type":"education","lineage":["https://openalex.org/I141945490"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Steve Wilton","raw_affiliation_strings":["The University of British Columbia, Vancouver, BC, Canada"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"The University of British Columbia, Vancouver, BC, Canada","institution_ids":["https://openalex.org/I141945490"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5107994859","display_name":"Philip H. W. Leong","orcid":"https://orcid.org/0000-0002-3923-3499"},"institutions":[{"id":"https://openalex.org/I129604602","display_name":"The University of Sydney","ror":"https://ror.org/0384j8v12","country_code":"AU","type":"education","lineage":["https://openalex.org/I129604602"]}],"countries":["AU"],"is_corresponding":false,"raw_author_name":"Philip H. W. Leong","raw_affiliation_strings":["The University of Sydney, NSW, Australia"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"The University of Sydney, NSW, Australia","institution_ids":["https://openalex.org/I129604602"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5040792997","display_name":"David Boland","orcid":"https://orcid.org/0000-0001-5370-4464"},"institutions":[{"id":"https://openalex.org/I129604602","display_name":"The University of Sydney","ror":"https://ror.org/0384j8v12","country_code":"AU","type":"education","lineage":["https://openalex.org/I129604602"]}],"countries":["AU"],"is_corresponding":false,"raw_author_name":"David Boland","raw_affiliation_strings":["The University of Sydney, NSW, Australia"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"The University of Sydney, NSW, Australia","institution_ids":["https://openalex.org/I129604602"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.15113126,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":95,"max":96},"biblio":{"volume":"15","issue":"1","first_page":"1","last_page":"30"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8544771671295166},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.697763979434967},{"id":"https://openalex.org/keywords/block","display_name":"Block (permutation group theory)","score":0.5744537711143494},{"id":"https://openalex.org/keywords/digital-signal-processing","display_name":"Digital signal processing","score":0.5613434910774231},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.5457243323326111},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4963095784187317},{"id":"https://openalex.org/keywords/parameterized-complexity","display_name":"Parameterized complexity","score":0.46420297026634216},{"id":"https://openalex.org/keywords/signal-processing","display_name":"Signal processing","score":0.46310704946517944},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.450950562953949},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.4276866316795349},{"id":"https://openalex.org/keywords/design-space-exploration","display_name":"Design space exploration","score":0.41088855266571045},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.34861481189727783},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.33077216148376465},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.2593495845794678}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8544771671295166},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.697763979434967},{"id":"https://openalex.org/C2777210771","wikidata":"https://www.wikidata.org/wiki/Q4927124","display_name":"Block (permutation group theory)","level":2,"score":0.5744537711143494},{"id":"https://openalex.org/C84462506","wikidata":"https://www.wikidata.org/wiki/Q173142","display_name":"Digital signal processing","level":2,"score":0.5613434910774231},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.5457243323326111},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4963095784187317},{"id":"https://openalex.org/C165464430","wikidata":"https://www.wikidata.org/wiki/Q1570441","display_name":"Parameterized complexity","level":2,"score":0.46420297026634216},{"id":"https://openalex.org/C104267543","wikidata":"https://www.wikidata.org/wiki/Q208163","display_name":"Signal processing","level":3,"score":0.46310704946517944},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.450950562953949},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.4276866316795349},{"id":"https://openalex.org/C2776221188","wikidata":"https://www.wikidata.org/wiki/Q21072556","display_name":"Design space exploration","level":2,"score":0.41088855266571045},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.34861481189727783},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.33077216148376465},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.2593495845794678},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/3491234","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3491234","pdf_url":null,"source":{"id":"https://openalex.org/S112809824","display_name":"ACM Transactions on Reconfigurable Technology and Systems","issn_l":"1936-7406","issn":["1936-7406","1936-7414"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319798","host_organization_name":"Association for Computing Machinery","host_organization_lineage":["https://openalex.org/P4310319798"],"host_organization_lineage_names":["Association for Computing Machinery"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"ACM Transactions on Reconfigurable Technology and Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","score":0.47999998927116394,"display_name":"Industry, innovation and infrastructure"}],"awards":[{"id":"https://openalex.org/G4587427570","display_name":null,"funder_award_id":"EP/S030069/1","funder_id":"https://openalex.org/F4320334627","funder_display_name":"Engineering and Physical Sciences Research Council"}],"funders":[{"id":"https://openalex.org/F4320334627","display_name":"Engineering and Physical Sciences Research Council","ror":"https://ror.org/0439y7842"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":25,"referenced_works":["https://openalex.org/W2061488635","https://openalex.org/W2094756095","https://openalex.org/W2194775991","https://openalex.org/W2583383421","https://openalex.org/W2792742540","https://openalex.org/W2903735800","https://openalex.org/W2913668833","https://openalex.org/W2916778556","https://openalex.org/W2918037051","https://openalex.org/W2949275038","https://openalex.org/W2983964638","https://openalex.org/W3001665736","https://openalex.org/W3008125474","https://openalex.org/W3008194216","https://openalex.org/W3008357423","https://openalex.org/W3022351289","https://openalex.org/W3027528898","https://openalex.org/W3033506121","https://openalex.org/W3046638030","https://openalex.org/W3101457918","https://openalex.org/W3131304503","https://openalex.org/W3163275603","https://openalex.org/W4287780544","https://openalex.org/W4288083474","https://openalex.org/W4288083528"],"related_works":["https://openalex.org/W4210376836","https://openalex.org/W1633995705","https://openalex.org/W2596211269","https://openalex.org/W197862639","https://openalex.org/W2360384790","https://openalex.org/W4232397253","https://openalex.org/W4235913033","https://openalex.org/W2109284253","https://openalex.org/W2039966832","https://openalex.org/W2359819289"],"abstract_inverted_index":{"The":[0,42],"underlying":[1],"goal":[2,69],"of":[3,17,45,53,70,127],"FPGA":[4,21,180],"architecture":[5,159,201],"research":[6],"is":[7,120,160,176],"to":[8,26,232],"devise":[9],"flexible":[10,143],"substrates":[11],"that":[12,175,187],"implement":[13],"a":[14,50,77,83,125,142,149,154,172],"wide":[15],"variety":[16],"circuits":[18],"efficiently.":[19],"Contemporary":[20],"architectures":[22,117],"have":[23],"been":[24],"optimized":[25],"support":[27,163],"networking,":[28],"signal":[29,38],"processing,":[30],"and":[31,61,101,169,205,207,222,227],"image":[32],"processing":[33,39],"applications":[34],"through":[35],"high-precision":[36],"digital":[37],"(DSP)":[40],"blocks.":[41],"recent":[43],"emergence":[44],"machine":[46],"learning":[47],"has":[48],"created":[49],"new":[51,73,128],"set":[52],"demands":[54],"characterized":[55],"by:":[56],"(1)":[57],"higher":[58,214],"computational":[59],"density":[60],"(2)":[62],"low":[63],"precision":[64],"arithmetic":[65],"requirements.":[66],"With":[67],"the":[68,197,219,235],"exploring":[71],"this":[72,238],"design":[74],"space":[75],"in":[76,153,237],"methodical":[78],"manner,":[79],"we":[80,185],"first":[81],"propose":[82],"problem":[84],"formulation":[85],"involving":[86],"computing":[87],"nested":[88],"loops":[89],"over":[90,196],"multiply-accumulate":[91,138],"(MAC)":[92],"operations,":[93],"which":[94],"covers":[95],"many":[96],"basic":[97],"linear":[98],"algebra":[99],"primitives":[100],"standard":[102],"deep":[103],"neural":[104],"network":[105],"(DNN)":[106],"kernels.":[107],"A":[108],"quantitative":[109],"methodology":[110],"for":[111,164,188,208],"deriving":[112],"efficient":[113],"coarse-grained":[114],"compute":[115],"block":[116],"from":[118],"benchmarks":[119],"then":[121],"proposed":[122],"together":[123],"with":[124,162,178,202,218,230],"family":[126],"embedded":[129],"blocks,":[130],"called":[131],"MLBlocks.":[132],"An":[133],"MLBlock":[134],"instance":[135],"includes":[136],"several":[137],"units":[139],"connected":[140],"via":[141],"routing,":[144],"where":[145],"each":[146],"configuration":[147],"performs":[148],"few":[150],"parallel":[151],"dot-products":[152],"systolic":[155],"array":[156],"fashion.":[157],"This":[158],"parameterized":[161],"different":[165],"data":[166],"movements,":[167],"reuse,":[168],"precisions,":[170],"utilizing":[171],"columnar":[173],"arrangement":[174],"compatible":[177],"existing":[179],"architectures.":[181],"On":[182],"synthetic":[183],"benchmarks,":[184],"demonstrate":[186],"8-bit":[189],"arithmetic,":[190,211],"MLBlocks":[191],"offer":[192],"6\u00d7":[193],"improved":[194],"performance":[195,215],"commercial":[198],"Xilinx":[199],"DSP48E2":[200],"smaller":[203],"area":[204,217,221],"delay;":[206],"time-multiplexed":[209],"16-bit":[210],"achieves":[212],"2\u00d7":[213],"per":[216],"same":[220],"frequency.":[223],"All":[224],"source":[225],"codes":[226],"data,":[228],"along":[229],"documents":[231],"reproduce":[233],"all":[234],"results":[236],"article,":[239],"are":[240],"available":[241],"at":[242],"http://github.com/raminrasoulinezhad/MLBlocks":[243],".":[244]},"counts_by_year":[{"year":2025,"cited_by_count":2}],"updated_date":"2026-05-21T06:26:12.895304","created_date":"2025-10-10T00:00:00"}