{"id":"https://openalex.org/W4225105027","doi":"https://doi.org/10.1145/3490422.3502335","title":"HiPR","display_name":"HiPR","publication_year":2022,"publication_date":"2022-02-11","ids":{"openalex":"https://openalex.org/W4225105027","doi":"https://doi.org/10.1145/3490422.3502335"},"language":"en","primary_location":{"id":"doi:10.1145/3490422.3502335","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3490422.3502335","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2022 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays","raw_type":"proceedings-article"},"type":"conference-abstract","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5078819157","display_name":"Yuanlong Xiao","orcid":"https://orcid.org/0000-0002-3749-2729"},"institutions":[{"id":"https://openalex.org/I79576946","display_name":"University of Pennsylvania","ror":"https://ror.org/00b30xv10","country_code":"US","type":"education","lineage":["https://openalex.org/I79576946"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Yuanlong Xiao","raw_affiliation_strings":["University of Pennsylvania, Philadelphia, PA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Pennsylvania, Philadelphia, PA, USA","institution_ids":["https://openalex.org/I79576946"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5087585086","display_name":"Andr\u00e9 DeHon","orcid":"https://orcid.org/0000-0001-9177-7699"},"institutions":[{"id":"https://openalex.org/I79576946","display_name":"University of Pennsylvania","ror":"https://ror.org/00b30xv10","country_code":"US","type":"education","lineage":["https://openalex.org/I79576946"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Andre DeHon","raw_affiliation_strings":["University of Pennsylvania, Philadelphia, PA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Pennsylvania, Philadelphia, PA, USA","institution_ids":["https://openalex.org/I79576946"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I79576946"],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"155","last_page":"155"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8412373065948486},{"id":"https://openalex.org/keywords/control-reconfiguration","display_name":"Control reconfiguration","score":0.7658215761184692},{"id":"https://openalex.org/keywords/high-level-synthesis","display_name":"High-level synthesis","score":0.7271007299423218},{"id":"https://openalex.org/keywords/debugging","display_name":"Debugging","score":0.6142658591270447},{"id":"https://openalex.org/keywords/compiler","display_name":"Compiler","score":0.5878312587738037},{"id":"https://openalex.org/keywords/floorplan","display_name":"Floorplan","score":0.5793750286102295},{"id":"https://openalex.org/keywords/verilog","display_name":"Verilog","score":0.5349760055541992},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5338550806045532},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.5163673162460327},{"id":"https://openalex.org/keywords/scheduling","display_name":"Scheduling (production processes)","score":0.44524097442626953},{"id":"https://openalex.org/keywords/coding","display_name":"Coding (social sciences)","score":0.4417160451412201},{"id":"https://openalex.org/keywords/static-timing-analysis","display_name":"Static timing analysis","score":0.4227392077445984},{"id":"https://openalex.org/keywords/compile-time","display_name":"Compile time","score":0.4147898256778717},{"id":"https://openalex.org/keywords/set","display_name":"Set (abstract data type)","score":0.4130121171474457},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4068417251110077},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.28036946058273315}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8412373065948486},{"id":"https://openalex.org/C119701452","wikidata":"https://www.wikidata.org/wiki/Q5165881","display_name":"Control reconfiguration","level":2,"score":0.7658215761184692},{"id":"https://openalex.org/C58013763","wikidata":"https://www.wikidata.org/wiki/Q5754574","display_name":"High-level synthesis","level":3,"score":0.7271007299423218},{"id":"https://openalex.org/C168065819","wikidata":"https://www.wikidata.org/wiki/Q845566","display_name":"Debugging","level":2,"score":0.6142658591270447},{"id":"https://openalex.org/C169590947","wikidata":"https://www.wikidata.org/wiki/Q47506","display_name":"Compiler","level":2,"score":0.5878312587738037},{"id":"https://openalex.org/C130145326","wikidata":"https://www.wikidata.org/wiki/Q1553985","display_name":"Floorplan","level":2,"score":0.5793750286102295},{"id":"https://openalex.org/C2779030575","wikidata":"https://www.wikidata.org/wiki/Q827773","display_name":"Verilog","level":3,"score":0.5349760055541992},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5338550806045532},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.5163673162460327},{"id":"https://openalex.org/C206729178","wikidata":"https://www.wikidata.org/wiki/Q2271896","display_name":"Scheduling (production processes)","level":2,"score":0.44524097442626953},{"id":"https://openalex.org/C179518139","wikidata":"https://www.wikidata.org/wiki/Q5140297","display_name":"Coding (social sciences)","level":2,"score":0.4417160451412201},{"id":"https://openalex.org/C93682380","wikidata":"https://www.wikidata.org/wiki/Q2025226","display_name":"Static timing analysis","level":2,"score":0.4227392077445984},{"id":"https://openalex.org/C200833197","wikidata":"https://www.wikidata.org/wiki/Q333707","display_name":"Compile time","level":3,"score":0.4147898256778717},{"id":"https://openalex.org/C177264268","wikidata":"https://www.wikidata.org/wiki/Q1514741","display_name":"Set (abstract data type)","level":2,"score":0.4130121171474457},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4068417251110077},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.28036946058273315},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C21547014","wikidata":"https://www.wikidata.org/wiki/Q1423657","display_name":"Operations management","level":1,"score":0.0},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/3490422.3502335","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3490422.3502335","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2022 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Decent work and economic growth","score":0.6200000047683716,"id":"https://metadata.un.org/sdg/8"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W3141861494","https://openalex.org/W2161004825","https://openalex.org/W2043900241","https://openalex.org/W2080729117","https://openalex.org/W1516038830","https://openalex.org/W2044534563","https://openalex.org/W2005854230","https://openalex.org/W2060497355","https://openalex.org/W2080804043","https://openalex.org/W2168113051"],"abstract_inverted_index":{"High-Level":[0],"Synthesis":[1],"can":[2,38,98,151,171],"abstract":[3],"away":[4],"low-level":[5,114],"circuits":[6],"design":[7],"and":[8,30,45,93,121,159],"improve":[9],"the":[10,17,28,40,47,50,68,79,89,118,123,131,142,153,161,167],"coding":[11],"productivity.":[12],"However,":[13],"it":[14],"also":[15,58],"lengthens":[16],"compilation":[18,41,51,169],"time,":[19],"exacerbating":[20],"an":[21],"already":[22],"slow":[23],"edit-compile-debug":[24],"loop":[25],"that":[26,71,87],"discourages":[27],"development":[29],"refinement":[31],"of":[32,49,145],"FPGA":[33],"accelerators.":[34],"Partial":[35],"Reconfiguration":[36],"techniques":[37],"decrease":[39],"time":[42,170],"by":[43,174],"reducing":[44],"parallelizing":[46],"size":[48],"task.":[52],"But":[53],"defining":[54],"partial":[55],"reconfigurable":[56,110],"regions":[57],"needs":[59],"expert":[60],"layout-level":[61],"knowledge,":[62],"making":[63],"this":[64],"approach":[65],"inaccessible":[66],"to":[67,75,125],"high-level":[69],"developers":[70],"HLS":[72,92],"is":[73],"intended":[74],"attract.":[76],"To":[77],"address":[78],"problems":[80],"above,":[81],"we":[82,148],"propose":[83],"HiPR,":[84,96],"a":[85,100,105],"framework":[86],"bridges":[88],"gap":[90],"between":[91],"PR.":[94],"With":[95],"users":[97,124],"define":[99,126],"C/C++":[101],"function":[102,134],"(rather":[103],"than":[104],"Verilog":[106],"module)":[107],"as":[108],"partially":[109],"without":[111],"considering":[112],"detailed":[113],"constraints.":[115],"HiPR":[116,150],"automates":[117],"PR":[119,133],"floorplan":[120,155],"allows":[122],"elastic":[127],"resource":[128],"requirements":[129],"for":[130,135,163],"C-level":[132],"quick":[136],"further":[137],"tuning":[138],"later.":[139],"By":[140],"mapping":[141],"full":[143],"set":[144],"Rosetta":[146],"Benchmarks,":[147],"show":[149],"find":[152],"proper":[154],"solution":[156],"within":[157],"seconds":[158],"generate":[160],"overlay":[162],"later":[164],"tuning.":[165],"Significantly,":[166],"incremental":[168],"be":[172],"accelerated":[173],"3-10X":[175],"with":[176],"no":[177],"performance":[178],"loss.":[179]},"counts_by_year":[{"year":2023,"cited_by_count":1}],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2022-04-30T00:00:00"}