{"id":"https://openalex.org/W4281621614","doi":"https://doi.org/10.1145/3470496.3527444","title":"SNS's not a synthesizer","display_name":"SNS's not a synthesizer","publication_year":2022,"publication_date":"2022-05-31","ids":{"openalex":"https://openalex.org/W4281621614","doi":"https://doi.org/10.1145/3470496.3527444"},"language":"en","primary_location":{"id":"doi:10.1145/3470496.3527444","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3470496.3527444","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 49th Annual International Symposium on Computer Architecture","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5036627994","display_name":"Ceyu Xu","orcid":"https://orcid.org/0000-0002-2668-6456"},"institutions":[{"id":"https://openalex.org/I170897317","display_name":"Duke University","ror":"https://ror.org/00py81415","country_code":"US","type":"education","lineage":["https://openalex.org/I170897317"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Ceyu Xu","raw_affiliation_strings":["Duke University"],"affiliations":[{"raw_affiliation_string":"Duke University","institution_ids":["https://openalex.org/I170897317"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5009440291","display_name":"Chris Kjellqvist","orcid":"https://orcid.org/0000-0002-4792-1910"},"institutions":[{"id":"https://openalex.org/I170897317","display_name":"Duke University","ror":"https://ror.org/00py81415","country_code":"US","type":"education","lineage":["https://openalex.org/I170897317"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Chris Kjellqvist","raw_affiliation_strings":["Duke University"],"affiliations":[{"raw_affiliation_string":"Duke University","institution_ids":["https://openalex.org/I170897317"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5042221799","display_name":"Lisa Wu Wills","orcid":"https://orcid.org/0000-0002-3574-3440"},"institutions":[{"id":"https://openalex.org/I170897317","display_name":"Duke University","ror":"https://ror.org/00py81415","country_code":"US","type":"education","lineage":["https://openalex.org/I170897317"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Lisa Wu Wills","raw_affiliation_strings":["Duke University"],"affiliations":[{"raw_affiliation_string":"Duke University","institution_ids":["https://openalex.org/I170897317"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5036627994"],"corresponding_institution_ids":["https://openalex.org/I170897317"],"apc_list":null,"apc_paid":null,"fwci":3.9682,"has_fulltext":false,"cited_by_count":20,"citation_normalized_percentile":{"value":0.94238018,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":97,"max":99},"biblio":{"volume":null,"issue":null,"first_page":"847","last_page":"859"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.6890451312065125},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.6252698302268982},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6013608574867249},{"id":"https://openalex.org/keywords/pace","display_name":"Pace","score":0.5898917317390442},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.5487726926803589},{"id":"https://openalex.org/keywords/moores-law","display_name":"Moore's law","score":0.5088596343994141},{"id":"https://openalex.org/keywords/transistor-count","display_name":"Transistor count","score":0.5080928802490234},{"id":"https://openalex.org/keywords/dimension","display_name":"Dimension (graph theory)","score":0.48860031366348267},{"id":"https://openalex.org/keywords/integrated-circuit-design","display_name":"Integrated circuit design","score":0.4777340590953827},{"id":"https://openalex.org/keywords/high-level-synthesis","display_name":"High-level synthesis","score":0.436862975358963},{"id":"https://openalex.org/keywords/physical-design","display_name":"Physical design","score":0.4194377660751343},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.41839799284935},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.4179399609565735},{"id":"https://openalex.org/keywords/circuit-design","display_name":"Circuit design","score":0.3657395839691162},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.2700512409210205},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.2474917471408844},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.18721219897270203},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.17574754357337952},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.09022322297096252},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.08711901307106018},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.07160839438438416}],"concepts":[{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.6890451312065125},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.6252698302268982},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6013608574867249},{"id":"https://openalex.org/C2777526511","wikidata":"https://www.wikidata.org/wiki/Q691543","display_name":"Pace","level":2,"score":0.5898917317390442},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.5487726926803589},{"id":"https://openalex.org/C206891323","wikidata":"https://www.wikidata.org/wiki/Q178655","display_name":"Moore's law","level":2,"score":0.5088596343994141},{"id":"https://openalex.org/C196320899","wikidata":"https://www.wikidata.org/wiki/Q2623746","display_name":"Transistor count","level":4,"score":0.5080928802490234},{"id":"https://openalex.org/C33676613","wikidata":"https://www.wikidata.org/wiki/Q13415176","display_name":"Dimension (graph theory)","level":2,"score":0.48860031366348267},{"id":"https://openalex.org/C74524168","wikidata":"https://www.wikidata.org/wiki/Q1074539","display_name":"Integrated circuit design","level":2,"score":0.4777340590953827},{"id":"https://openalex.org/C58013763","wikidata":"https://www.wikidata.org/wiki/Q5754574","display_name":"High-level synthesis","level":3,"score":0.436862975358963},{"id":"https://openalex.org/C188817802","wikidata":"https://www.wikidata.org/wiki/Q13426855","display_name":"Physical design","level":3,"score":0.4194377660751343},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.41839799284935},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4179399609565735},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.3657395839691162},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.2700512409210205},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.2474917471408844},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.18721219897270203},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.17574754357337952},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.09022322297096252},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.08711901307106018},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.07160839438438416},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C13280743","wikidata":"https://www.wikidata.org/wiki/Q131089","display_name":"Geodesy","level":1,"score":0.0},{"id":"https://openalex.org/C205649164","wikidata":"https://www.wikidata.org/wiki/Q1071","display_name":"Geography","level":0,"score":0.0},{"id":"https://openalex.org/C202444582","wikidata":"https://www.wikidata.org/wiki/Q837863","display_name":"Pure mathematics","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1145/3470496.3527444","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3470496.3527444","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 49th Annual International Symposium on Computer Architecture","raw_type":"proceedings-article"},{"id":"pmh:oai:repository.hkust.edu.hk:1783.1-169981","is_oa":false,"landing_page_url":"http://repository.hkust.edu.hk/ir/Record/1783.1-169981","pdf_url":null,"source":{"id":"https://openalex.org/S4306401796","display_name":"Rare & Special e-Zone (The Hong Kong University of Science and Technology)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I200769079","host_organization_name":"Hong Kong University of Science and Technology","host_organization_lineage":["https://openalex.org/I200769079"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"Conference paper"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[{"id":"https://openalex.org/G2248245597","display_name":null,"funder_award_id":"2045974","funder_id":"https://openalex.org/F4320306076","funder_display_name":"National Science Foundation"}],"funders":[{"id":"https://openalex.org/F4320306076","display_name":"National Science Foundation","ror":"https://ror.org/021nxhr62"},{"id":"https://openalex.org/F4320306087","display_name":"Semiconductor Research Corporation","ror":"https://ror.org/047z4n946"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":27,"referenced_works":["https://openalex.org/W1983394510","https://openalex.org/W2012114780","https://openalex.org/W2054095206","https://openalex.org/W2079751107","https://openalex.org/W2154851992","https://openalex.org/W2588191434","https://openalex.org/W2916991310","https://openalex.org/W2945802982","https://openalex.org/W2946795101","https://openalex.org/W2964121744","https://openalex.org/W2964268978","https://openalex.org/W2980282514","https://openalex.org/W2985324865","https://openalex.org/W3005387090","https://openalex.org/W3008874958","https://openalex.org/W3013164405","https://openalex.org/W3017521908","https://openalex.org/W3027968530","https://openalex.org/W3091933103","https://openalex.org/W3092027164","https://openalex.org/W3104097132","https://openalex.org/W3112616759","https://openalex.org/W3116677748","https://openalex.org/W3177277791","https://openalex.org/W3212867926","https://openalex.org/W4231250608","https://openalex.org/W4253012315"],"related_works":["https://openalex.org/W2543290882","https://openalex.org/W2735446578","https://openalex.org/W2246407281","https://openalex.org/W4253195573","https://openalex.org/W2115118594","https://openalex.org/W2366617252","https://openalex.org/W2017475176","https://openalex.org/W2020934033","https://openalex.org/W2143407223","https://openalex.org/W4281621614"],"abstract_inverted_index":{"The":[0],"number":[1],"of":[2,16,28,100],"transistors":[3],"that":[4,41],"can":[5],"fit":[6],"on":[7],"one":[8],"monolithic":[9],"chip":[10,36,70],"has":[11],"reached":[12],"billions":[13,17],"to":[14,22,54,83,90,96],"tens":[15],"in":[18,46,63],"this":[19],"decade":[20],"thanks":[21],"Moore's":[23],"Law.":[24],"With":[25],"the":[26,32,50],"advancement":[27],"every":[29],"technology":[30],"generation,":[31],"transistor":[33],"counts":[34],"per":[35],"grow":[37],"at":[38],"a":[39,60],"pace":[40],"brings":[42],"about":[43],"exponential":[44],"increase":[45],"design":[47,56,88],"time,":[48],"including":[49],"synthesis":[51,65,106],"process":[52],"used":[53],"perform":[55],"space":[57],"explorations.":[58],"Such":[59],"long":[61],"delay":[62],"obtaining":[64],"results":[66],"hinders":[67],"an":[68],"efficient":[69],"development":[71],"process,":[72],"significantly":[73],"impacting":[74],"time-to-market.":[75],"In":[76],"addition,":[77],"these":[78],"large-scale":[79],"integrated":[80],"circuits":[81],"tend":[82],"have":[84],"larger":[85],"and":[86],"higher-dimension":[87],"spaces":[89],"explore,":[91],"making":[92],"it":[93],"prohibitively":[94],"expensive":[95],"obtain":[97],"physical":[98],"characteristics":[99],"all":[101],"possible":[102],"designs":[103],"using":[104],"traditional":[105],"tools.":[107]},"counts_by_year":[{"year":2026,"cited_by_count":3},{"year":2025,"cited_by_count":7},{"year":2024,"cited_by_count":4},{"year":2023,"cited_by_count":6}],"updated_date":"2026-04-21T08:09:41.155169","created_date":"2025-10-10T00:00:00"}