{"id":"https://openalex.org/W3185867486","doi":"https://doi.org/10.1145/3462632","title":"Monolithically Integrating Non-Volatile Main Memory over the Last-Level Cache","display_name":"Monolithically Integrating Non-Volatile Main Memory over the Last-Level Cache","publication_year":2021,"publication_date":"2021-07-17","ids":{"openalex":"https://openalex.org/W3185867486","doi":"https://doi.org/10.1145/3462632","mag":"3185867486"},"language":"en","primary_location":{"id":"doi:10.1145/3462632","is_oa":true,"landing_page_url":"https://doi.org/10.1145/3462632","pdf_url":"https://dl.acm.org/doi/pdf/10.1145/3462632","source":{"id":"https://openalex.org/S26056741","display_name":"ACM Transactions on Architecture and Code Optimization","issn_l":"1544-3566","issn":["1544-3566","1544-3973"],"is_oa":true,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319798","host_organization_name":"Association for Computing Machinery","host_organization_lineage":["https://openalex.org/P4310319798"],"host_organization_lineage_names":["Association for Computing Machinery"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"ACM Transactions on Architecture and Code Optimization","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"diamond","oa_url":"https://dl.acm.org/doi/pdf/10.1145/3462632","any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5078737041","display_name":"Candace Walden","orcid":"https://orcid.org/0000-0003-0367-1179"},"institutions":[{"id":"https://openalex.org/I66946132","display_name":"University of Maryland, College Park","ror":"https://ror.org/047s2c258","country_code":"US","type":"education","lineage":["https://openalex.org/I66946132"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Candace Walden","raw_affiliation_strings":["University of Maryland, College Park"],"affiliations":[{"raw_affiliation_string":"University of Maryland, College Park","institution_ids":["https://openalex.org/I66946132"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5108756456","display_name":"Devesh Singh","orcid":null},"institutions":[{"id":"https://openalex.org/I66946132","display_name":"University of Maryland, College Park","ror":"https://ror.org/047s2c258","country_code":"US","type":"education","lineage":["https://openalex.org/I66946132"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Devesh Singh","raw_affiliation_strings":["University of Maryland, College Park"],"affiliations":[{"raw_affiliation_string":"University of Maryland, College Park","institution_ids":["https://openalex.org/I66946132"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5060574158","display_name":"Meenatchi Jagasivamani","orcid":null},"institutions":[{"id":"https://openalex.org/I66946132","display_name":"University of Maryland, College Park","ror":"https://ror.org/047s2c258","country_code":"US","type":"education","lineage":["https://openalex.org/I66946132"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Meenatchi Jagasivamani","raw_affiliation_strings":["University of Maryland, College Park"],"affiliations":[{"raw_affiliation_string":"University of Maryland, College Park","institution_ids":["https://openalex.org/I66946132"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5004722925","display_name":"Li Shang","orcid":"https://orcid.org/0000-0003-3944-7531"},"institutions":[{"id":"https://openalex.org/I66946132","display_name":"University of Maryland, College Park","ror":"https://ror.org/047s2c258","country_code":"US","type":"education","lineage":["https://openalex.org/I66946132"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Shang Li","raw_affiliation_strings":["University of Maryland, College Park"],"affiliations":[{"raw_affiliation_string":"University of Maryland, College Park","institution_ids":["https://openalex.org/I66946132"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5017493298","display_name":"Luyi Kang","orcid":"https://orcid.org/0009-0001-8510-5551"},"institutions":[{"id":"https://openalex.org/I66946132","display_name":"University of Maryland, College Park","ror":"https://ror.org/047s2c258","country_code":"US","type":"education","lineage":["https://openalex.org/I66946132"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Luyi Kang","raw_affiliation_strings":["University of Maryland, College Park"],"affiliations":[{"raw_affiliation_string":"University of Maryland, College Park","institution_ids":["https://openalex.org/I66946132"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5007682067","display_name":"Mehdi Asnaashari","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Mehdi Asnaashari","raw_affiliation_strings":["Crossbar Inc"],"affiliations":[{"raw_affiliation_string":"Crossbar Inc","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5059912566","display_name":"Sylvain Dubois","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Sylvain Dubois","raw_affiliation_strings":["Crossbar Inc"],"affiliations":[{"raw_affiliation_string":"Crossbar Inc","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5047597896","display_name":"Bruce Jacob","orcid":"https://orcid.org/0009-0005-3493-8245"},"institutions":[{"id":"https://openalex.org/I66946132","display_name":"University of Maryland, College Park","ror":"https://ror.org/047s2c258","country_code":"US","type":"education","lineage":["https://openalex.org/I66946132"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Bruce Jacob","raw_affiliation_strings":["University of Maryland, College Park"],"affiliations":[{"raw_affiliation_string":"University of Maryland, College Park","institution_ids":["https://openalex.org/I66946132"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5042239243","display_name":"Donald Yeung","orcid":"https://orcid.org/0000-0003-0341-2644"},"institutions":[{"id":"https://openalex.org/I66946132","display_name":"University of Maryland, College Park","ror":"https://ror.org/047s2c258","country_code":"US","type":"education","lineage":["https://openalex.org/I66946132"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Donald Yeung","raw_affiliation_strings":["University of Maryland, College Park"],"affiliations":[{"raw_affiliation_string":"University of Maryland, College Park","institution_ids":["https://openalex.org/I66946132"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":9,"corresponding_author_ids":["https://openalex.org/A5078737041"],"corresponding_institution_ids":["https://openalex.org/I66946132"],"apc_list":null,"apc_paid":null,"fwci":1.3817,"has_fulltext":true,"cited_by_count":8,"citation_normalized_percentile":{"value":0.80088356,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":95,"max":97},"biblio":{"volume":"18","issue":"4","first_page":"1","last_page":"26"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7654394507408142},{"id":"https://openalex.org/keywords/memory-controller","display_name":"Memory controller","score":0.6836467981338501},{"id":"https://openalex.org/keywords/registered-memory","display_name":"Registered memory","score":0.5980797410011292},{"id":"https://openalex.org/keywords/memory-map","display_name":"Memory map","score":0.5501431226730347},{"id":"https://openalex.org/keywords/interleaved-memory","display_name":"Interleaved memory","score":0.5307854413986206},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.49036312103271484},{"id":"https://openalex.org/keywords/cpu-cache","display_name":"CPU cache","score":0.47503143548965454},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.47380250692367554},{"id":"https://openalex.org/keywords/non-uniform-memory-access","display_name":"Non-uniform memory access","score":0.47249141335487366},{"id":"https://openalex.org/keywords/conventional-memory","display_name":"Conventional memory","score":0.4712921679019928},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.4605393409729004},{"id":"https://openalex.org/keywords/cache-only-memory-architecture","display_name":"Cache-only memory architecture","score":0.46048861742019653},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.43744704127311707},{"id":"https://openalex.org/keywords/interface","display_name":"Interface (matter)","score":0.4262087345123291},{"id":"https://openalex.org/keywords/central-processing-unit","display_name":"Central processing unit","score":0.4217485785484314},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.41847527027130127},{"id":"https://openalex.org/keywords/dram","display_name":"Dram","score":0.41792696714401245},{"id":"https://openalex.org/keywords/memory-refresh","display_name":"Memory refresh","score":0.4153668284416199},{"id":"https://openalex.org/keywords/non-volatile-memory","display_name":"Non-volatile memory","score":0.41077983379364014},{"id":"https://openalex.org/keywords/computer-memory","display_name":"Computer memory","score":0.40375304222106934}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7654394507408142},{"id":"https://openalex.org/C100800780","wikidata":"https://www.wikidata.org/wiki/Q1175867","display_name":"Memory controller","level":3,"score":0.6836467981338501},{"id":"https://openalex.org/C93446704","wikidata":"https://www.wikidata.org/wiki/Q449328","display_name":"Registered memory","level":3,"score":0.5980797410011292},{"id":"https://openalex.org/C74426580","wikidata":"https://www.wikidata.org/wiki/Q719484","display_name":"Memory map","level":3,"score":0.5501431226730347},{"id":"https://openalex.org/C63511323","wikidata":"https://www.wikidata.org/wiki/Q908936","display_name":"Interleaved memory","level":4,"score":0.5307854413986206},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.49036312103271484},{"id":"https://openalex.org/C189783530","wikidata":"https://www.wikidata.org/wiki/Q352090","display_name":"CPU cache","level":3,"score":0.47503143548965454},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.47380250692367554},{"id":"https://openalex.org/C133371097","wikidata":"https://www.wikidata.org/wiki/Q868014","display_name":"Non-uniform memory access","level":5,"score":0.47249141335487366},{"id":"https://openalex.org/C53838383","wikidata":"https://www.wikidata.org/wiki/Q541148","display_name":"Conventional memory","level":5,"score":0.4712921679019928},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4605393409729004},{"id":"https://openalex.org/C3720319","wikidata":"https://www.wikidata.org/wiki/Q5015937","display_name":"Cache-only memory architecture","level":5,"score":0.46048861742019653},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.43744704127311707},{"id":"https://openalex.org/C113843644","wikidata":"https://www.wikidata.org/wiki/Q901882","display_name":"Interface (matter)","level":4,"score":0.4262087345123291},{"id":"https://openalex.org/C49154492","wikidata":"https://www.wikidata.org/wiki/Q5300","display_name":"Central processing unit","level":2,"score":0.4217485785484314},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.41847527027130127},{"id":"https://openalex.org/C7366592","wikidata":"https://www.wikidata.org/wiki/Q1255620","display_name":"Dram","level":2,"score":0.41792696714401245},{"id":"https://openalex.org/C87907426","wikidata":"https://www.wikidata.org/wiki/Q6815755","display_name":"Memory refresh","level":4,"score":0.4153668284416199},{"id":"https://openalex.org/C177950962","wikidata":"https://www.wikidata.org/wiki/Q10997658","display_name":"Non-volatile memory","level":2,"score":0.41077983379364014},{"id":"https://openalex.org/C92855701","wikidata":"https://www.wikidata.org/wiki/Q5830907","display_name":"Computer memory","level":3,"score":0.40375304222106934},{"id":"https://openalex.org/C129307140","wikidata":"https://www.wikidata.org/wiki/Q6795880","display_name":"Maximum bubble pressure method","level":3,"score":0.0},{"id":"https://openalex.org/C157915830","wikidata":"https://www.wikidata.org/wiki/Q2928001","display_name":"Bubble","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/3462632","is_oa":true,"landing_page_url":"https://doi.org/10.1145/3462632","pdf_url":"https://dl.acm.org/doi/pdf/10.1145/3462632","source":{"id":"https://openalex.org/S26056741","display_name":"ACM Transactions on Architecture and Code Optimization","issn_l":"1544-3566","issn":["1544-3566","1544-3973"],"is_oa":true,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319798","host_organization_name":"Association for Computing Machinery","host_organization_lineage":["https://openalex.org/P4310319798"],"host_organization_lineage_names":["Association for Computing Machinery"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"ACM Transactions on Architecture and Code Optimization","raw_type":"journal-article"}],"best_oa_location":{"id":"doi:10.1145/3462632","is_oa":true,"landing_page_url":"https://doi.org/10.1145/3462632","pdf_url":"https://dl.acm.org/doi/pdf/10.1145/3462632","source":{"id":"https://openalex.org/S26056741","display_name":"ACM Transactions on Architecture and Code Optimization","issn_l":"1544-3566","issn":["1544-3566","1544-3973"],"is_oa":true,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319798","host_organization_name":"Association for Computing Machinery","host_organization_lineage":["https://openalex.org/P4310319798"],"host_organization_lineage_names":["Association for Computing Machinery"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"ACM Transactions on Architecture and Code Optimization","raw_type":"journal-article"},"sustainable_development_goals":[{"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7","score":0.8700000047683716}],"awards":[],"funders":[{"id":"https://openalex.org/F4320306087","display_name":"Semiconductor Research Corporation","ror":"https://ror.org/047z4n946"}],"has_content":{"pdf":true,"grobid_xml":true},"content_urls":{"pdf":"https://content.openalex.org/works/W3185867486.pdf","grobid_xml":"https://content.openalex.org/works/W3185867486.grobid-xml"},"referenced_works_count":38,"referenced_works":["https://openalex.org/W1482680420","https://openalex.org/W1583642359","https://openalex.org/W1955235267","https://openalex.org/W2010202670","https://openalex.org/W2013028205","https://openalex.org/W2027895023","https://openalex.org/W2034062945","https://openalex.org/W2048508570","https://openalex.org/W2080592089","https://openalex.org/W2086874410","https://openalex.org/W2088207049","https://openalex.org/W2104305170","https://openalex.org/W2112753327","https://openalex.org/W2113235308","https://openalex.org/W2114139104","https://openalex.org/W2147539449","https://openalex.org/W2154001575","https://openalex.org/W2160428323","https://openalex.org/W2161522487","https://openalex.org/W2162651880","https://openalex.org/W2169150396","https://openalex.org/W2169863928","https://openalex.org/W2209394967","https://openalex.org/W2340522713","https://openalex.org/W2899741796","https://openalex.org/W2907909057","https://openalex.org/W2913899326","https://openalex.org/W2914895134","https://openalex.org/W2975723806","https://openalex.org/W2982726777","https://openalex.org/W3006586535","https://openalex.org/W3027606857","https://openalex.org/W3105011558","https://openalex.org/W3123793361","https://openalex.org/W4205474951","https://openalex.org/W4206010581","https://openalex.org/W4229800208","https://openalex.org/W4239813889"],"related_works":["https://openalex.org/W3108993429","https://openalex.org/W2782503170","https://openalex.org/W1982632559","https://openalex.org/W2041174925","https://openalex.org/W2047684617","https://openalex.org/W4233816696","https://openalex.org/W1975698617","https://openalex.org/W1979830285","https://openalex.org/W4321458411","https://openalex.org/W2168550483"],"abstract_inverted_index":{"Many":[0],"emerging":[1],"non-volatile":[2,28],"memories":[3,29],"are":[4],"compatible":[5],"with":[6],"CMOS":[7],"logic,":[8],"potentially":[9],"enabling":[10],"their":[11],"integration":[12,164],"into":[13],"a":[14,69,76,91,109,226],"CPU\u2019s":[15,44],"die.":[16],"This":[17],"article":[18],"investigates":[19],"such":[20,34],"monolithically":[21],"integrated":[22],"CPU\u2013main":[23],"memory":[24,62,72,87,100,136,151,169,190,223],"chips.":[25],"We":[26,66,102,121],"exploit":[27],"employing":[30],"3D":[31,114],"crosspoint":[32],"subarrays,":[33],"as":[35],"resistive":[36],"RAM":[37],"(ReRAM),":[38],"and":[39,59,85,89,98,128,146,167,174,182,195,215,218],"integrate":[40],"them":[41],"over":[42,116,176],"the":[43,57,83,126,133,139,189,202,208,221],"last-level":[45],"cache":[46,52,84],"(LLC).":[47],"The":[48,148],"regular":[49],"structure":[50],"of":[51,56,125,132,141,165,205],"arrays":[53],"enables":[54],"co-design":[55,124,206],"LLC":[58,97,119,127],"ReRAM":[60,115,129],"main":[61,86,99,168,216],"for":[63,81,179],"area":[64,137,203],"efficiency.":[65],"also":[67,187],"develop":[68],"streamlined":[70,149],"LLC/main":[71,150,222],"interface":[73,152,224],"that":[74,123,201,219],"employs":[75],"single":[77],"shared":[78],"internal":[79],"interconnect":[80],"both":[82,96],"arrays,":[88],"uses":[90],"unified":[92],"controller":[93],"to":[94,108,210],"service":[95],"requests.":[101],"apply":[103],"our":[104],"monolithic":[105,163],"design":[106],"ideas":[107],"many-core":[110],"CPU":[111,166,209],"by":[112,172,193],"integrating":[113],"each":[117],"core\u2019s":[118],"slice.":[120],"find":[122],"saves":[130,153],"27%":[131],"total":[134],"LLC\u2013main":[135],"at":[138],"expense":[140],"slight":[142],"increases":[143],"in":[144,157],"delay":[145],"energy.":[147],"an":[154],"additional":[155],"12%":[156],"area.":[158],"Our":[159],"simulation":[160],"results":[161],"show":[162,200],"improves":[170],"performance":[171,229],"5.3\u00d7":[173],"1.7\u00d7":[175],"HBM2":[177],"DRAM":[178],"several":[180],"graph":[181],"streaming":[183],"kernels,":[184],"respectively.":[185,197],"It":[186],"reduces":[188],"system\u2019s":[191],"energy":[192],"6.0\u00d7":[194],"1.7\u00d7,":[196],"Moreover,":[198],"we":[199],"savings":[204],"permits":[207],"have":[211],"23%":[212],"more":[213],"cores":[214],"memory,":[217],"streamlining":[220],"incurs":[225],"small":[227],"4%":[228],"penalty.":[230]},"counts_by_year":[{"year":2025,"cited_by_count":2},{"year":2024,"cited_by_count":3},{"year":2023,"cited_by_count":3}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}