{"id":"https://openalex.org/W3201891881","doi":"https://doi.org/10.1145/3458744.3473353","title":"Intra- and Inter- Layer Transformation to Reduce Memory Traffic for CNN Computation","display_name":"Intra- and Inter- Layer Transformation to Reduce Memory Traffic for CNN Computation","publication_year":2021,"publication_date":"2021-08-09","ids":{"openalex":"https://openalex.org/W3201891881","doi":"https://doi.org/10.1145/3458744.3473353","mag":"3201891881"},"language":"en","primary_location":{"id":"doi:10.1145/3458744.3473353","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3458744.3473353","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"50th International Conference on Parallel Processing Workshop","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5031068445","display_name":"Pin-Wei Liao","orcid":null},"institutions":[{"id":"https://openalex.org/I16733864","display_name":"National Taiwan University","ror":"https://ror.org/05bqach95","country_code":"TW","type":"education","lineage":["https://openalex.org/I16733864"]}],"countries":["TW"],"is_corresponding":true,"raw_author_name":"Pin-Wei Liao","raw_affiliation_strings":["National Taiwan University"],"affiliations":[{"raw_affiliation_string":"National Taiwan University","institution_ids":["https://openalex.org/I16733864"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5017207899","display_name":"Wei\u2010Chung Hsu","orcid":"https://orcid.org/0000-0002-0833-7981"},"institutions":[{"id":"https://openalex.org/I16733864","display_name":"National Taiwan University","ror":"https://ror.org/05bqach95","country_code":"TW","type":"education","lineage":["https://openalex.org/I16733864"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Wei-Chung Hsu","raw_affiliation_strings":["National Taiwan University, Taiwan"],"affiliations":[{"raw_affiliation_string":"National Taiwan University, Taiwan","institution_ids":["https://openalex.org/I16733864"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5113826583","display_name":"Shih-Wei Liao","orcid":null},"institutions":[{"id":"https://openalex.org/I16733864","display_name":"National Taiwan University","ror":"https://ror.org/05bqach95","country_code":"TW","type":"education","lineage":["https://openalex.org/I16733864"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Shih-Wei Liao","raw_affiliation_strings":["National Taiwan University"],"affiliations":[{"raw_affiliation_string":"National Taiwan University","institution_ids":["https://openalex.org/I16733864"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5031068445"],"corresponding_institution_ids":["https://openalex.org/I16733864"],"apc_list":null,"apc_paid":null,"fwci":0.1003,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.43505448,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":"1","issue":null,"first_page":"1","last_page":"5"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10036","display_name":"Advanced Neural Network Applications","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/1707","display_name":"Computer Vision and Pattern Recognition"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12808","display_name":"Ferroelectric and Negative Capacitance Devices","score":0.9980999827384949,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/dram","display_name":"Dram","score":0.8729065656661987},{"id":"https://openalex.org/keywords/static-random-access-memory","display_name":"Static random-access memory","score":0.8300194144248962},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7581727504730225},{"id":"https://openalex.org/keywords/enhanced-data-rates-for-gsm-evolution","display_name":"Enhanced Data Rates for GSM Evolution","score":0.5404004454612732},{"id":"https://openalex.org/keywords/computation","display_name":"Computation","score":0.5379688143730164},{"id":"https://openalex.org/keywords/universal-memory","display_name":"Universal memory","score":0.5018622875213623},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.49584874510765076},{"id":"https://openalex.org/keywords/key","display_name":"Key (lock)","score":0.47819140553474426},{"id":"https://openalex.org/keywords/transformation","display_name":"Transformation (genetics)","score":0.4755646586418152},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.4751041829586029},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.43995341658592224},{"id":"https://openalex.org/keywords/random-access-memory","display_name":"Random access memory","score":0.43833574652671814},{"id":"https://openalex.org/keywords/layer","display_name":"Layer (electronics)","score":0.4265179932117462},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4030718207359314},{"id":"https://openalex.org/keywords/memory-management","display_name":"Memory management","score":0.3580952286720276},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3120626211166382},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.2204279899597168},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.17040538787841797},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.1611204445362091},{"id":"https://openalex.org/keywords/interleaved-memory","display_name":"Interleaved memory","score":0.10908648371696472},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.09463158249855042}],"concepts":[{"id":"https://openalex.org/C7366592","wikidata":"https://www.wikidata.org/wiki/Q1255620","display_name":"Dram","level":2,"score":0.8729065656661987},{"id":"https://openalex.org/C68043766","wikidata":"https://www.wikidata.org/wiki/Q267416","display_name":"Static random-access memory","level":2,"score":0.8300194144248962},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7581727504730225},{"id":"https://openalex.org/C162307627","wikidata":"https://www.wikidata.org/wiki/Q204833","display_name":"Enhanced Data Rates for GSM Evolution","level":2,"score":0.5404004454612732},{"id":"https://openalex.org/C45374587","wikidata":"https://www.wikidata.org/wiki/Q12525525","display_name":"Computation","level":2,"score":0.5379688143730164},{"id":"https://openalex.org/C195053848","wikidata":"https://www.wikidata.org/wiki/Q7894141","display_name":"Universal memory","level":5,"score":0.5018622875213623},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.49584874510765076},{"id":"https://openalex.org/C26517878","wikidata":"https://www.wikidata.org/wiki/Q228039","display_name":"Key (lock)","level":2,"score":0.47819140553474426},{"id":"https://openalex.org/C204241405","wikidata":"https://www.wikidata.org/wiki/Q461499","display_name":"Transformation (genetics)","level":3,"score":0.4755646586418152},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4751041829586029},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.43995341658592224},{"id":"https://openalex.org/C2994168587","wikidata":"https://www.wikidata.org/wiki/Q5295","display_name":"Random access memory","level":2,"score":0.43833574652671814},{"id":"https://openalex.org/C2779227376","wikidata":"https://www.wikidata.org/wiki/Q6505497","display_name":"Layer (electronics)","level":2,"score":0.4265179932117462},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4030718207359314},{"id":"https://openalex.org/C176649486","wikidata":"https://www.wikidata.org/wiki/Q2308807","display_name":"Memory management","level":3,"score":0.3580952286720276},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3120626211166382},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.2204279899597168},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.17040538787841797},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.1611204445362091},{"id":"https://openalex.org/C63511323","wikidata":"https://www.wikidata.org/wiki/Q908936","display_name":"Interleaved memory","level":4,"score":0.10908648371696472},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.09463158249855042},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C55493867","wikidata":"https://www.wikidata.org/wiki/Q7094","display_name":"Biochemistry","level":1,"score":0.0},{"id":"https://openalex.org/C178790620","wikidata":"https://www.wikidata.org/wiki/Q11351","display_name":"Organic chemistry","level":1,"score":0.0},{"id":"https://openalex.org/C185592680","wikidata":"https://www.wikidata.org/wiki/Q2329","display_name":"Chemistry","level":0,"score":0.0},{"id":"https://openalex.org/C104317684","wikidata":"https://www.wikidata.org/wiki/Q7187","display_name":"Gene","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/3458744.3473353","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3458744.3473353","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"50th International Conference on Parallel Processing Workshop","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":10,"referenced_works":["https://openalex.org/W1633637678","https://openalex.org/W2194775991","https://openalex.org/W2204300687","https://openalex.org/W2442974303","https://openalex.org/W2605487586","https://openalex.org/W2911936770","https://openalex.org/W2913059114","https://openalex.org/W2979644612","https://openalex.org/W3015441707","https://openalex.org/W4234392772"],"related_works":["https://openalex.org/W2094308961","https://openalex.org/W1974599144","https://openalex.org/W370196896","https://openalex.org/W4386903460","https://openalex.org/W2793465010","https://openalex.org/W2533585248","https://openalex.org/W2186356227","https://openalex.org/W3205888584","https://openalex.org/W2125880695","https://openalex.org/W2541005978"],"abstract_inverted_index":{"Edge":[0],"inference":[1],"has":[2],"gained":[3],"much":[4],"popularity":[5],"in":[6],"recent":[7],"years.":[8],"Many":[9],"AI":[10,40],"accelerators":[11],"have":[12],"been":[13],"proposed":[14],"and":[15,31],"extensively":[16],"studied.":[17],"Such":[18],"devices":[19],"are":[20],"often":[21],"packed":[22],"with":[23],"a":[24],"large":[25],"number":[26],"of":[27,33],"PEs":[28],"(Processing":[29],"Elements),":[30],"lots":[32],"on-chip":[34,54],"SRAM.":[35,55],"The":[36],"key":[37],"to":[38,43,52],"successful":[39],"acceleration":[41],"is":[42],"effectively":[44],"use":[45],"the":[46,53],"data":[47],"transferred":[48],"from":[49],"off-chip":[50],"DRAM":[51]},"counts_by_year":[{"year":2022,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}