{"id":"https://openalex.org/W3204203797","doi":"https://doi.org/10.1145/3458744.3473348","title":"Hyperchaining Optimizations for an LLVM-Based Binary Translator on x86-64 and RISC-V Platforms","display_name":"Hyperchaining Optimizations for an LLVM-Based Binary Translator on x86-64 and RISC-V Platforms","publication_year":2021,"publication_date":"2021-08-09","ids":{"openalex":"https://openalex.org/W3204203797","doi":"https://doi.org/10.1145/3458744.3473348","mag":"3204203797"},"language":"en","primary_location":{"id":"doi:10.1145/3458744.3473348","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3458744.3473348","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"50th International Conference on Parallel Processing Workshop","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5077691128","display_name":"Jyun-Kai Lai","orcid":null},"institutions":[{"id":"https://openalex.org/I148366613","display_name":"National Yang Ming Chiao Tung University","ror":"https://ror.org/00se2k293","country_code":"TW","type":"education","lineage":["https://openalex.org/I148366613"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Jyun-Kai Lai","raw_affiliation_strings":["National Yang Ming Chiao Tung University, Taiwan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"National Yang Ming Chiao Tung University, Taiwan","institution_ids":["https://openalex.org/I148366613"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5077494496","display_name":"Wuu Yang","orcid":"https://orcid.org/0000-0001-8913-5662"},"institutions":[{"id":"https://openalex.org/I148366613","display_name":"National Yang Ming Chiao Tung University","ror":"https://ror.org/00se2k293","country_code":"TW","type":"education","lineage":["https://openalex.org/I148366613"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Wuu Yang","raw_affiliation_strings":["National Yang Ming Chiao Tung University, Taiwan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"National Yang Ming Chiao Tung University, Taiwan","institution_ids":["https://openalex.org/I148366613"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I148366613"],"apc_list":null,"apc_paid":null,"fwci":0.4465,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.52786984,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":95},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"9"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9988999962806702,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9983000159263611,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/x86","display_name":"x86","score":0.9415536522865295},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.803754448890686},{"id":"https://openalex.org/keywords/speedup","display_name":"Speedup","score":0.7376950979232788},{"id":"https://openalex.org/keywords/leverage","display_name":"Leverage (statistics)","score":0.6766107082366943},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.6314185261726379},{"id":"https://openalex.org/keywords/overhead","display_name":"Overhead (engineering)","score":0.5791217088699341},{"id":"https://openalex.org/keywords/instruction-set","display_name":"Instruction set","score":0.5472545027732849},{"id":"https://openalex.org/keywords/reduced-instruction-set-computing","display_name":"Reduced instruction set computing","score":0.491643488407135},{"id":"https://openalex.org/keywords/binary-number","display_name":"Binary number","score":0.44878438115119934},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.41700878739356995},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3749659061431885},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.2267221212387085},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.07429489493370056}],"concepts":[{"id":"https://openalex.org/C170723468","wikidata":"https://www.wikidata.org/wiki/Q182933","display_name":"x86","level":3,"score":0.9415536522865295},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.803754448890686},{"id":"https://openalex.org/C68339613","wikidata":"https://www.wikidata.org/wiki/Q1549489","display_name":"Speedup","level":2,"score":0.7376950979232788},{"id":"https://openalex.org/C153083717","wikidata":"https://www.wikidata.org/wiki/Q6535263","display_name":"Leverage (statistics)","level":2,"score":0.6766107082366943},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.6314185261726379},{"id":"https://openalex.org/C2779960059","wikidata":"https://www.wikidata.org/wiki/Q7113681","display_name":"Overhead (engineering)","level":2,"score":0.5791217088699341},{"id":"https://openalex.org/C202491316","wikidata":"https://www.wikidata.org/wiki/Q272683","display_name":"Instruction set","level":2,"score":0.5472545027732849},{"id":"https://openalex.org/C126298526","wikidata":"https://www.wikidata.org/wiki/Q189376","display_name":"Reduced instruction set computing","level":3,"score":0.491643488407135},{"id":"https://openalex.org/C48372109","wikidata":"https://www.wikidata.org/wiki/Q3913","display_name":"Binary number","level":2,"score":0.44878438115119934},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.41700878739356995},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3749659061431885},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.2267221212387085},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.07429489493370056},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C94375191","wikidata":"https://www.wikidata.org/wiki/Q11205","display_name":"Arithmetic","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/3458744.3473348","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3458744.3473348","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"50th International Conference on Parallel Processing Workshop","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy","score":0.47999998927116394}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":8,"referenced_works":["https://openalex.org/W2001723134","https://openalex.org/W2064391085","https://openalex.org/W2081101824","https://openalex.org/W2107075183","https://openalex.org/W2325071780","https://openalex.org/W2573835612","https://openalex.org/W2603355854","https://openalex.org/W2963356946"],"related_works":["https://openalex.org/W1966837078","https://openalex.org/W2045177269","https://openalex.org/W2126497765","https://openalex.org/W2116582200","https://openalex.org/W2538644970","https://openalex.org/W4376881175","https://openalex.org/W4297336601","https://openalex.org/W4310584696","https://openalex.org/W3027553599","https://openalex.org/W2439357447"],"abstract_inverted_index":{"Rabbit":[0,21],"is":[1],"an":[2],"LLVM-based":[3],"hybrid":[4],"binary":[5],"translator":[6],"with":[7,77,101],"many":[8],"diverse":[9],"optimizations":[10,41],"to":[11,17,47],"improve":[12],"the":[13,49,53,66],"performance.":[14],"In":[15],"addition":[16],"platform-independent":[18,78,102],"hyperchaining":[19,25,68,79,93],"(indep),":[20],"also":[22,89],"includes":[23],"platform-dependent":[24,67,92],"(dep)":[26],"on":[27],"both":[28,34],"x86-64":[29],"and":[30,36,45,72,82],"RISC-V":[31],"architectures":[32],"for":[33,80],"direct":[35,81],"indirect":[37,83],"branches.":[38],"The":[39,61,86],"dep":[40],"leverage":[42],"architecture-specific":[43],"instructions":[44],"patches":[46],"achieve":[48,70],"same":[50],"effect":[51],"as":[52],"indep":[54],"optimiztion":[55],"but":[56],"gains":[57],"more":[58],"performance":[59],"improvement.":[60],"experimental":[62,87],"results":[63,88],"show":[64,90],"that":[65,91],"can":[69],"1.08x":[71],"1.05x":[73],"speedup":[74],"in":[75,99],"comparison":[76,100],"branches,":[84],"respectively.":[85],"incurs":[94],"little":[95],"memory":[96],"space":[97],"overhead":[98],"hyperchaining.":[103]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2024,"cited_by_count":1},{"year":2022,"cited_by_count":1}],"updated_date":"2026-07-30T17:31:21.811387","created_date":"2025-10-10T00:00:00"}
