{"id":"https://openalex.org/W3120107135","doi":"https://doi.org/10.1145/3432261.3432266","title":"Performance Evaluation of OpenCL-Enabled Inter-FPGA Optical Link Communication Framework CIRCUS and SMI","display_name":"Performance Evaluation of OpenCL-Enabled Inter-FPGA Optical Link Communication Framework CIRCUS and SMI","publication_year":2021,"publication_date":"2021-01-14","ids":{"openalex":"https://openalex.org/W3120107135","doi":"https://doi.org/10.1145/3432261.3432266","mag":"3120107135"},"language":"en","primary_location":{"id":"doi:10.1145/3432261.3432266","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3432261.3432266","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"The International Conference on High Performance Computing in Asia-Pacific Region","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5089674286","display_name":"Ryuta Kashino","orcid":null},"institutions":[{"id":"https://openalex.org/I146399215","display_name":"University of Tsukuba","ror":"https://ror.org/02956yf07","country_code":"JP","type":"education","lineage":["https://openalex.org/I146399215"]}],"countries":["JP"],"is_corresponding":true,"raw_author_name":"Ryuta Kashino","raw_affiliation_strings":["University of Tsukuba, Japan"],"affiliations":[{"raw_affiliation_string":"University of Tsukuba, Japan","institution_ids":["https://openalex.org/I146399215"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5000110706","display_name":"Ryohei Kobayashi","orcid":"https://orcid.org/0000-0003-2175-9828"},"institutions":[{"id":"https://openalex.org/I146399215","display_name":"University of Tsukuba","ror":"https://ror.org/02956yf07","country_code":"JP","type":"education","lineage":["https://openalex.org/I146399215"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Ryohei Kobayashi","raw_affiliation_strings":["University of Tsukuba, Japan"],"affiliations":[{"raw_affiliation_string":"University of Tsukuba, Japan","institution_ids":["https://openalex.org/I146399215"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5084940217","display_name":"Norihisa Fujita","orcid":"https://orcid.org/0000-0002-5386-7623"},"institutions":[{"id":"https://openalex.org/I146399215","display_name":"University of Tsukuba","ror":"https://ror.org/02956yf07","country_code":"JP","type":"education","lineage":["https://openalex.org/I146399215"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Norihisa Fujita","raw_affiliation_strings":["University of Tsukuba, Japan"],"affiliations":[{"raw_affiliation_string":"University of Tsukuba, Japan","institution_ids":["https://openalex.org/I146399215"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5020716792","display_name":"Taisuke Boku","orcid":"https://orcid.org/0000-0001-8730-2228"},"institutions":[{"id":"https://openalex.org/I146399215","display_name":"University of Tsukuba","ror":"https://ror.org/02956yf07","country_code":"JP","type":"education","lineage":["https://openalex.org/I146399215"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Taisuke Boku","raw_affiliation_strings":["University of Tsukuba, Japan"],"affiliations":[{"raw_affiliation_string":"University of Tsukuba, Japan","institution_ids":["https://openalex.org/I146399215"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5089674286"],"corresponding_institution_ids":["https://openalex.org/I146399215"],"apc_list":null,"apc_paid":null,"fwci":0.4062,"has_fulltext":false,"cited_by_count":4,"citation_normalized_percentile":{"value":0.58968318,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":95},"biblio":{"volume":null,"issue":null,"first_page":"23","last_page":"31"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10299","display_name":"Photonic and Optical Devices","score":0.9980000257492065,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10299","display_name":"Photonic and Optical Devices","score":0.9980000257492065,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9972000122070312,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9958999752998352,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.9466465711593628},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8047050833702087},{"id":"https://openalex.org/keywords/construct","display_name":"Construct (python library)","score":0.6261699199676514},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.53404301404953},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.499819278717041},{"id":"https://openalex.org/keywords/bandwidth","display_name":"Bandwidth (computing)","score":0.4872699975967407},{"id":"https://openalex.org/keywords/reconfigurable-computing","display_name":"Reconfigurable computing","score":0.4812347888946533},{"id":"https://openalex.org/keywords/gate-array","display_name":"Gate array","score":0.43179407715797424},{"id":"https://openalex.org/keywords/supercomputer","display_name":"Supercomputer","score":0.4115251302719116},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.2418540120124817},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.09362420439720154}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.9466465711593628},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8047050833702087},{"id":"https://openalex.org/C2780801425","wikidata":"https://www.wikidata.org/wiki/Q5164392","display_name":"Construct (python library)","level":2,"score":0.6261699199676514},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.53404301404953},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.499819278717041},{"id":"https://openalex.org/C2776257435","wikidata":"https://www.wikidata.org/wiki/Q1576430","display_name":"Bandwidth (computing)","level":2,"score":0.4872699975967407},{"id":"https://openalex.org/C142962650","wikidata":"https://www.wikidata.org/wiki/Q240838","display_name":"Reconfigurable computing","level":3,"score":0.4812347888946533},{"id":"https://openalex.org/C114237110","wikidata":"https://www.wikidata.org/wiki/Q114901","display_name":"Gate array","level":3,"score":0.43179407715797424},{"id":"https://openalex.org/C83283714","wikidata":"https://www.wikidata.org/wiki/Q121117","display_name":"Supercomputer","level":2,"score":0.4115251302719116},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.2418540120124817},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.09362420439720154}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1145/3432261.3432266","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3432261.3432266","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"The International Conference on High Performance Computing in Asia-Pacific Region","raw_type":"proceedings-article"},{"id":"pmh:oai:t2r2.star.titech.ac.jp:50719602","is_oa":false,"landing_page_url":"http://t2r2.star.titech.ac.jp/cgi-bin/publicationinfo.cgi?q_publication_content_number=CTT100927013","pdf_url":null,"source":{"id":"https://openalex.org/S4377196385","display_name":"Tokyo Tech Research Repository (Tokyo Institute of Technology)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I114531698","host_organization_name":"Tokyo Institute of Technology","host_organization_lineage":["https://openalex.org/I114531698"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"Conference Paper"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.47999998927116394,"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure"}],"awards":[{"id":"https://openalex.org/G359556276","display_name":null,"funder_award_id":"Next Generation High-Performance Computing Infrastructures and Applications R&D Program","funder_id":"https://openalex.org/F4320320912","funder_display_name":"Ministry of Education, Culture, Sports, Science and Technology"},{"id":"https://openalex.org/G4454983236","display_name":null,"funder_award_id":"18H03246","funder_id":"https://openalex.org/F4320334764","funder_display_name":"Japan Society for the Promotion of Science"}],"funders":[{"id":"https://openalex.org/F4320320912","display_name":"Ministry of Education, Culture, Sports, Science and Technology","ror":"https://ror.org/048rj2z13"},{"id":"https://openalex.org/F4320334764","display_name":"Japan Society for the Promotion of Science","ror":"https://ror.org/00hhkn466"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":6,"referenced_works":["https://openalex.org/W2889426436","https://openalex.org/W2966634689","https://openalex.org/W2983676609","https://openalex.org/W2994835017","https://openalex.org/W3046893044","https://openalex.org/W4288086140"],"related_works":["https://openalex.org/W1612076744","https://openalex.org/W2126857316","https://openalex.org/W2152074211","https://openalex.org/W2129019972","https://openalex.org/W3164085601","https://openalex.org/W1522032972","https://openalex.org/W4399458808","https://openalex.org/W2113308450","https://openalex.org/W1967938402","https://openalex.org/W2143386935"],"abstract_inverted_index":{"In":[0],"recent":[1],"years,":[2],"Field":[3],"Programmable":[4],"Gate":[5],"Array":[6],"(FPGAs)":[7],"have":[8],"attracted":[9],"much":[10],"attention":[11],"as":[12,47,49],"accelerators":[13],"in":[14],"the":[15,24],"research":[16],"area":[17],"of":[18,23,27],"HighPerformance":[19],"Computing":[20],"(HPC).":[21],"One":[22],"strong":[25],"features":[26],"current":[28],"FPGA":[29,53],"devices":[30],"is":[31,55],"their":[32,50],"ability":[33],"to":[34,43,71],"achieve":[35],"high-bandwidth":[36],"communication":[37],"performance":[38],"with":[39],"direct":[40],"optical":[41],"links":[42],"construct":[44],"multi-FPGA":[45,76],"platforms":[46],"well":[48],"adjustability.":[51],"However,":[52],"programming":[54,65],"not":[56],"easily":[57],"performed":[58],"on":[59,75],"user":[60],"applications.":[61],"By":[62],"more":[63],"user-friendly":[64],"environments,":[66],"FPGAs":[67],"can":[68],"be":[69],"applied":[70],"various":[72],"HPC":[73],"applications":[74],"platforms.":[77]},"counts_by_year":[{"year":2023,"cited_by_count":1},{"year":2022,"cited_by_count":1},{"year":2021,"cited_by_count":2}],"updated_date":"2026-04-05T17:49:38.594831","created_date":"2025-10-10T00:00:00"}