{"id":"https://openalex.org/W3129912126","doi":"https://doi.org/10.1145/3431920.3439302","title":"FABulous: An Embedded FPGA Framework","display_name":"FABulous: An Embedded FPGA Framework","publication_year":2021,"publication_date":"2021-02-17","ids":{"openalex":"https://openalex.org/W3129912126","doi":"https://doi.org/10.1145/3431920.3439302","mag":"3129912126"},"language":"en","primary_location":{"id":"doi:10.1145/3431920.3439302","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3431920.3439302","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"The 2021 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5064000482","display_name":"Dirk Koch","orcid":"https://orcid.org/0000-0002-2568-4432"},"institutions":[{"id":"https://openalex.org/I28407311","display_name":"University of Manchester","ror":"https://ror.org/027m9bs27","country_code":"GB","type":"education","lineage":["https://openalex.org/I28407311"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Dirk Koch","raw_affiliation_strings":["The University of Manchester, Manchester, United Kingdom"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"The University of Manchester, Manchester, United Kingdom","institution_ids":["https://openalex.org/I28407311"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5068422348","display_name":"Nguyen Cong Dao","orcid":"https://orcid.org/0000-0003-2775-9503"},"institutions":[{"id":"https://openalex.org/I28407311","display_name":"University of Manchester","ror":"https://ror.org/027m9bs27","country_code":"GB","type":"education","lineage":["https://openalex.org/I28407311"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Nguyen Dao","raw_affiliation_strings":["The University of Manchester, Manchester, United Kingdom"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"The University of Manchester, Manchester, United Kingdom","institution_ids":["https://openalex.org/I28407311"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5007595487","display_name":"Bea Healy","orcid":null},"institutions":[{"id":"https://openalex.org/I28407311","display_name":"University of Manchester","ror":"https://ror.org/027m9bs27","country_code":"GB","type":"education","lineage":["https://openalex.org/I28407311"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Bea Healy","raw_affiliation_strings":["The University of Manchester, Manchester, United Kingdom"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"The University of Manchester, Manchester, United Kingdom","institution_ids":["https://openalex.org/I28407311"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5088934264","display_name":"Jing Yu","orcid":"https://orcid.org/0000-0001-8792-7201"},"institutions":[{"id":"https://openalex.org/I28407311","display_name":"University of Manchester","ror":"https://ror.org/027m9bs27","country_code":"GB","type":"education","lineage":["https://openalex.org/I28407311"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Jing Yu","raw_affiliation_strings":["The University of Manchester, Manchester, United Kingdom"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"The University of Manchester, Manchester, United Kingdom","institution_ids":["https://openalex.org/I28407311"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5037013475","display_name":"Andrew Attwood","orcid":null},"institutions":[{"id":"https://openalex.org/I63098007","display_name":"Liverpool John Moores University","ror":"https://ror.org/04zfme737","country_code":"GB","type":"education","lineage":["https://openalex.org/I63098007"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Andrew Attwood","raw_affiliation_strings":["Liverpool John Moores University, Liverpool, United Kingdom"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Liverpool John Moores University, Liverpool, United Kingdom","institution_ids":["https://openalex.org/I63098007"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":3.6612,"has_fulltext":false,"cited_by_count":60,"citation_normalized_percentile":{"value":0.93519421,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":100},"biblio":{"volume":null,"issue":null,"first_page":"45","last_page":"56"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7769126892089844},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7684723138809204},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.7466632127761841},{"id":"https://openalex.org/keywords/application-specific-integrated-circuit","display_name":"Application-specific integrated circuit","score":0.6267008781433105},{"id":"https://openalex.org/keywords/fpga-prototype","display_name":"FPGA prototype","score":0.5201162099838257},{"id":"https://openalex.org/keywords/software-portability","display_name":"Software portability","score":0.5046905279159546},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.4817385971546173},{"id":"https://openalex.org/keywords/porting","display_name":"Porting","score":0.45194271206855774},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.44584691524505615},{"id":"https://openalex.org/keywords/emulation","display_name":"Emulation","score":0.4451172947883606},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.409220814704895},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.2537335157394409},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.20933830738067627}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7769126892089844},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7684723138809204},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.7466632127761841},{"id":"https://openalex.org/C77390884","wikidata":"https://www.wikidata.org/wiki/Q217302","display_name":"Application-specific integrated circuit","level":2,"score":0.6267008781433105},{"id":"https://openalex.org/C203864433","wikidata":"https://www.wikidata.org/wiki/Q5426992","display_name":"FPGA prototype","level":3,"score":0.5201162099838257},{"id":"https://openalex.org/C63000827","wikidata":"https://www.wikidata.org/wiki/Q3080428","display_name":"Software portability","level":2,"score":0.5046905279159546},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.4817385971546173},{"id":"https://openalex.org/C106251023","wikidata":"https://www.wikidata.org/wiki/Q851989","display_name":"Porting","level":3,"score":0.45194271206855774},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.44584691524505615},{"id":"https://openalex.org/C149810388","wikidata":"https://www.wikidata.org/wiki/Q5374873","display_name":"Emulation","level":2,"score":0.4451172947883606},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.409220814704895},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.2537335157394409},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.20933830738067627},{"id":"https://openalex.org/C50522688","wikidata":"https://www.wikidata.org/wiki/Q189833","display_name":"Economic growth","level":1,"score":0.0},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/3431920.3439302","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3431920.3439302","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"The 2021 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[{"id":"https://openalex.org/G5977211707","display_name":"Functional Oxide Reconfigurable Technologies (FORTE): A Programme Grant","funder_award_id":"EP/R024642/1","funder_id":"https://openalex.org/F4320334627","funder_display_name":"Engineering and Physical Sciences Research Council"},{"id":"https://openalex.org/G6097759542","display_name":null,"funder_award_id":"EP/R024642/1","funder_id":"https://openalex.org/F4320334627","funder_display_name":"Engineering and Physical Sciences Research Council"}],"funders":[{"id":"https://openalex.org/F4320334627","display_name":"Engineering and Physical Sciences Research Council","ror":"https://ror.org/0439y7842"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":38,"referenced_works":["https://openalex.org/W589238424","https://openalex.org/W600520643","https://openalex.org/W1480183640","https://openalex.org/W1524957862","https://openalex.org/W1669114967","https://openalex.org/W1984105700","https://openalex.org/W1996689269","https://openalex.org/W2005602803","https://openalex.org/W2024415338","https://openalex.org/W2096132155","https://openalex.org/W2111427553","https://openalex.org/W2115133259","https://openalex.org/W2116094656","https://openalex.org/W2130276110","https://openalex.org/W2134890772","https://openalex.org/W2138840350","https://openalex.org/W2139637699","https://openalex.org/W2142737439","https://openalex.org/W2157367913","https://openalex.org/W2157855196","https://openalex.org/W2162628682","https://openalex.org/W2165099691","https://openalex.org/W2168493238","https://openalex.org/W2604877941","https://openalex.org/W2612354329","https://openalex.org/W2770020066","https://openalex.org/W2948541259","https://openalex.org/W2951713654","https://openalex.org/W2951749218","https://openalex.org/W3007361144","https://openalex.org/W3027559990","https://openalex.org/W3160646870","https://openalex.org/W4236815763","https://openalex.org/W4383754359","https://openalex.org/W6677165070","https://openalex.org/W6730190348","https://openalex.org/W6737351731","https://openalex.org/W6764362099"],"related_works":["https://openalex.org/W1820309981","https://openalex.org/W3124707092","https://openalex.org/W2375332572","https://openalex.org/W28826848","https://openalex.org/W3123383020","https://openalex.org/W2152694830","https://openalex.org/W2912579397","https://openalex.org/W2166776054","https://openalex.org/W4312942606","https://openalex.org/W2373446736"],"abstract_inverted_index":{"At":[0],"the":[1,5,28,47,58,83,120,139],"end":[2],"of":[3,7,30,60,62,82],"CMOS-scaling,":[4],"role":[6],"architecture":[8],"design":[9],"is":[10,38,54],"increasingly":[11],"gaining":[12],"importance.":[13],"Supporting":[14],"this":[15],"trend,":[16],"customizable":[17],"embedded":[18,49,121,167],"FPGAs":[19],"are":[20,45],"an":[21,149,159,166,181],"ingredient":[22],"in":[23],"ASIC":[24,160],"architectures":[25],"to":[26,56,66,107],"provide":[27,148],"advantages":[29],"reconfigurable":[31],"hardware":[32],"exactly":[33],"where":[34],"and":[35,74,79,95,114,131,142,180],"how":[36],"it":[37],"most":[39],"beneficial.":[40],"To":[41],"enable":[42],"this,":[43],"we":[44,147],"introducing":[46],"FABulous":[48,53,117,155],"open-source":[50,182],"FPGA":[51,85,122,134,168],"framework.":[52],"designed":[55],"fulfill":[57],"objectives":[59],"ease":[61],"use,":[63],"maximum":[64],"portability":[65],"different":[67],"process":[68,179,184],"nodes,":[69],"good":[70,76],"control":[71],"for":[72,91,124,152,158,170],"customization,":[73],"delivering":[75],"area,":[77],"power,":[78],"performance":[80],"characteristics":[81],"generated":[84],"fabrics.":[86],"The":[87,116],"framework":[88],"provides":[89],"templates":[90],"logic,":[92],"arithmetic,":[93],"memory,":[94],"I/O":[96],"blocks":[97,113],"that":[98],"can":[99],"be":[100],"easily":[101],"stitched":[102],"together,":[103],"whilst":[104],"enabling":[105],"users":[106],"add":[108],"their":[109],"own":[110],"fully":[111],"customized":[112],"primitives.":[115],"ecosystem":[118],"generates":[119],"fabric":[123,169],"chip":[125],"fabrication,":[126],"integrates":[127],"Yosys,":[128],"ABC,":[129],"VPR":[130],"nextpnr":[132],"as":[133],"CAD":[135],"tools,":[136],"deals":[137],"with":[138,165],"bitstream":[140],"generation":[141],"after":[143],"fabrication":[144],"tests.":[145],"Additionally,":[146],"emulation":[150],"path":[151],"system":[153],"development.":[154],"was":[156],"demonstrated":[157],"integrating":[161],"a":[162,176],"RISC-V":[163],"core":[164],"custom":[171],"instruction":[172],"set":[173],"extensions":[174],"using":[175],"TSMC":[177],"180nm":[178],"45nm":[183],"node.":[185]},"counts_by_year":[{"year":2026,"cited_by_count":4},{"year":2025,"cited_by_count":19},{"year":2024,"cited_by_count":11},{"year":2023,"cited_by_count":9},{"year":2022,"cited_by_count":9},{"year":2021,"cited_by_count":7},{"year":2020,"cited_by_count":1}],"updated_date":"2026-06-19T17:40:00.097472","created_date":"2025-10-10T00:00:00"}