{"id":"https://openalex.org/W3113850555","doi":"https://doi.org/10.1145/3430699","title":"A Distributed Hardware Monitoring System for Runtime Verification on Multi-Tile MPSoCs","display_name":"A Distributed Hardware Monitoring System for Runtime Verification on Multi-Tile MPSoCs","publication_year":2020,"publication_date":"2020-12-30","ids":{"openalex":"https://openalex.org/W3113850555","doi":"https://doi.org/10.1145/3430699","mag":"3113850555"},"language":"en","primary_location":{"id":"doi:10.1145/3430699","is_oa":true,"landing_page_url":"https://doi.org/10.1145/3430699","pdf_url":"https://dl.acm.org/doi/pdf/10.1145/3430699","source":{"id":"https://openalex.org/S26056741","display_name":"ACM Transactions on Architecture and Code Optimization","issn_l":"1544-3566","issn":["1544-3566","1544-3973"],"is_oa":true,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319798","host_organization_name":"Association for Computing Machinery","host_organization_lineage":["https://openalex.org/P4310319798"],"host_organization_lineage_names":["Association for Computing Machinery"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"ACM Transactions on Architecture and Code Optimization","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"diamond","oa_url":"https://dl.acm.org/doi/pdf/10.1145/3430699","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5030024548","display_name":"Marcel Mettler","orcid":"https://orcid.org/0000-0002-7183-485X"},"institutions":[{"id":"https://openalex.org/I62916508","display_name":"Technical University of Munich","ror":"https://ror.org/02kkvpp62","country_code":"DE","type":"education","lineage":["https://openalex.org/I62916508"]}],"countries":["DE"],"is_corresponding":true,"raw_author_name":"Marcel Mettler","raw_affiliation_strings":["Chair of EDA, Technical University of Munich"],"raw_orcid":"https://orcid.org/0000-0002-7183-485X","affiliations":[{"raw_affiliation_string":"Chair of EDA, Technical University of Munich","institution_ids":["https://openalex.org/I62916508"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5011419637","display_name":"Daniel Mueller-Gritschneder","orcid":"https://orcid.org/0000-0003-0903-631X"},"institutions":[{"id":"https://openalex.org/I62916508","display_name":"Technical University of Munich","ror":"https://ror.org/02kkvpp62","country_code":"DE","type":"education","lineage":["https://openalex.org/I62916508"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Daniel Mueller-Gritschneder","raw_affiliation_strings":["Chair of EDA, Technical University of Munich"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Chair of EDA, Technical University of Munich","institution_ids":["https://openalex.org/I62916508"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5017567485","display_name":"Ulf Schlichtmann","orcid":"https://orcid.org/0000-0003-4431-7619"},"institutions":[{"id":"https://openalex.org/I62916508","display_name":"Technical University of Munich","ror":"https://ror.org/02kkvpp62","country_code":"DE","type":"education","lineage":["https://openalex.org/I62916508"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Ulf Schlichtmann","raw_affiliation_strings":["Chair of EDA, Technical University of Munich"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Chair of EDA, Technical University of Munich","institution_ids":["https://openalex.org/I62916508"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5030024548"],"corresponding_institution_ids":["https://openalex.org/I62916508"],"apc_list":null,"apc_paid":null,"fwci":0.4716,"has_fulltext":true,"cited_by_count":4,"citation_normalized_percentile":{"value":0.63404315,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":98},"biblio":{"volume":"18","issue":"1","first_page":"1","last_page":"25"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10142","display_name":"Formal Methods in Verification","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/mpsoc","display_name":"MPSoC","score":0.9060819745063782},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8539146780967712},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.6181768774986267},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.6176290512084961},{"id":"https://openalex.org/keywords/overhead","display_name":"Overhead (engineering)","score":0.533348560333252},{"id":"https://openalex.org/keywords/tracing","display_name":"Tracing","score":0.48568710684776306},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.46285122632980347},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3462088108062744},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3348122239112854},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.1360085904598236}],"concepts":[{"id":"https://openalex.org/C2777187653","wikidata":"https://www.wikidata.org/wiki/Q975106","display_name":"MPSoC","level":3,"score":0.9060819745063782},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8539146780967712},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6181768774986267},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.6176290512084961},{"id":"https://openalex.org/C2779960059","wikidata":"https://www.wikidata.org/wiki/Q7113681","display_name":"Overhead (engineering)","level":2,"score":0.533348560333252},{"id":"https://openalex.org/C138673069","wikidata":"https://www.wikidata.org/wiki/Q322229","display_name":"Tracing","level":2,"score":0.48568710684776306},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.46285122632980347},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3462088108062744},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3348122239112854},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.1360085904598236}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1145/3430699","is_oa":true,"landing_page_url":"https://doi.org/10.1145/3430699","pdf_url":"https://dl.acm.org/doi/pdf/10.1145/3430699","source":{"id":"https://openalex.org/S26056741","display_name":"ACM Transactions on Architecture and Code Optimization","issn_l":"1544-3566","issn":["1544-3566","1544-3973"],"is_oa":true,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319798","host_organization_name":"Association for Computing Machinery","host_organization_lineage":["https://openalex.org/P4310319798"],"host_organization_lineage_names":["Association for Computing Machinery"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"ACM Transactions on Architecture and Code Optimization","raw_type":"journal-article"},{"id":"pmh:oai:mediatum.ub.tum.de:node/1659351","is_oa":true,"landing_page_url":"https://mediatum.ub.tum.de/1659351","pdf_url":null,"source":{"id":"https://openalex.org/S4377196330","display_name":"mediaTUM  (Technical University of Munich)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I62916508","host_organization_name":"Technical University of Munich","host_organization_lineage":["https://openalex.org/I62916508"],"host_organization_lineage_names":[],"type":"repository"},"license":"other-oa","license_id":"https://openalex.org/licenses/other-oa","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"article"}],"best_oa_location":{"id":"doi:10.1145/3430699","is_oa":true,"landing_page_url":"https://doi.org/10.1145/3430699","pdf_url":"https://dl.acm.org/doi/pdf/10.1145/3430699","source":{"id":"https://openalex.org/S26056741","display_name":"ACM Transactions on Architecture and Code Optimization","issn_l":"1544-3566","issn":["1544-3566","1544-3973"],"is_oa":true,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319798","host_organization_name":"Association for Computing Machinery","host_organization_lineage":["https://openalex.org/P4310319798"],"host_organization_lineage_names":["Association for Computing Machinery"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"ACM Transactions on Architecture and Code Optimization","raw_type":"journal-article"},"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","score":0.5,"id":"https://metadata.un.org/sdg/9"}],"awards":[{"id":"https://openalex.org/G554679937","display_name":null,"funder_award_id":"146371743","funder_id":"https://openalex.org/F4320320879","funder_display_name":"Deutsche Forschungsgemeinschaft"},{"id":"https://openalex.org/G7265854623","display_name":null,"funder_award_id":"TRR 89","funder_id":"https://openalex.org/F4320320879","funder_display_name":"Deutsche Forschungsgemeinschaft"},{"id":"https://openalex.org/G7372727324","display_name":null,"funder_award_id":"146371743-TRR 89","funder_id":"https://openalex.org/F4320320879","funder_display_name":"Deutsche Forschungsgemeinschaft"}],"funders":[{"id":"https://openalex.org/F4320320879","display_name":"Deutsche Forschungsgemeinschaft","ror":"https://ror.org/018mejw64"}],"has_content":{"grobid_xml":true,"pdf":true},"content_urls":{"pdf":"https://content.openalex.org/works/W3113850555.pdf","grobid_xml":"https://content.openalex.org/works/W3113850555.grobid-xml"},"referenced_works_count":24,"referenced_works":["https://openalex.org/W64030814","https://openalex.org/W1580560707","https://openalex.org/W1980360906","https://openalex.org/W2027769154","https://openalex.org/W2062949766","https://openalex.org/W2079727599","https://openalex.org/W2087382815","https://openalex.org/W2101623441","https://openalex.org/W2112121929","https://openalex.org/W2151607777","https://openalex.org/W2153567586","https://openalex.org/W2166778115","https://openalex.org/W2170741679","https://openalex.org/W2493205813","https://openalex.org/W2594609971","https://openalex.org/W2753231957","https://openalex.org/W2785852717","https://openalex.org/W2888285544","https://openalex.org/W2899781265","https://openalex.org/W2979875482","https://openalex.org/W3033703179","https://openalex.org/W4248570190","https://openalex.org/W4253554348","https://openalex.org/W4255941490"],"related_works":["https://openalex.org/W2502691491","https://openalex.org/W1976012348","https://openalex.org/W2002682434","https://openalex.org/W2137671689","https://openalex.org/W4387782849","https://openalex.org/W2113449380","https://openalex.org/W2012131147","https://openalex.org/W2157008728","https://openalex.org/W2092587530","https://openalex.org/W2014331820"],"abstract_inverted_index":{"Exhaustive":[0],"verification":[1,17],"techniques":[2],"do":[3],"not":[4],"scale":[5],"with":[6,146],"the":[7,27,34,102,105,125,133],"complexity":[8],"of":[9,30,98,104,127],"today\u2019s":[10],"multi-tile":[11,49],"Multi-processor":[12],"Systems-on-chip":[13],"(MPSoCs).":[14],"Hence,":[15],"runtime":[16],"(RV)":[18],"has":[19,89],"emerged":[20],"as":[21],"a":[22,43,63,71,90,94,143,151],"complementary":[23],"method,":[24],"which":[25,101],"verifies":[26],"correct":[28],"behavior":[29,103],"applications":[31],"executed":[32],"on":[33,93,100,150],"MPSoC":[35,145],"during":[36],"runtime.":[37],"In":[38,51],"this":[39],"article,":[40],"we":[41,61,117],"propose":[42,62,118],"decentralized":[44],"monitoring":[45,138],"architecture":[46,139],"for":[47,59,124,142],"large-scale":[48],"MPSoCs.":[50],"order":[52],"to":[53,83,129,131],"minimize":[54],"performance":[55],"and":[56,65,78,113],"power":[57],"overhead":[58],"RV,":[60],"lightweight":[64],"non-intrusive":[66],"hardware":[67],"solution.":[68],"It":[69],"features":[70],"new":[72],"specialized":[73],"tracing":[74],"interconnect":[75],"that":[76],"distributes":[77],"sorts":[79],"detected":[80],"events":[81,99],"according":[82],"their":[84],"timestamps.":[85],"Each":[86],"tile":[87],"monitor":[88],"consistent":[91],"view":[92],"globally":[95],"sorted":[96],"trace":[97],"target":[106],"application":[107],"can":[108],"be":[109],"verified":[110],"using":[111],"logical":[112],"timing":[114],"requirements.":[115],"Furthermore,":[116],"an":[119],"integer":[120],"linear":[121],"programming-based":[122],"algorithm":[123],"assignment":[126],"requirements":[128],"monitors":[130],"exploit":[132],"local":[134],"resources":[135],"best.":[136],"The":[137],"is":[140],"demonstrated":[141],"four-tiled":[144],"20":[147],"cores":[148],"implemented":[149],"Virtex-7":[152],"field-programmable":[153],"gate":[154],"array":[155],"(FPGA).":[156]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2024,"cited_by_count":1},{"year":2022,"cited_by_count":1},{"year":2021,"cited_by_count":1}],"updated_date":"2026-05-05T08:41:31.759640","created_date":"2025-10-10T00:00:00"}