{"id":"https://openalex.org/W3111509700","doi":"https://doi.org/10.1145/3414622.3432992","title":"Wafer scale interconnect and pathfinding for machine learning hardware (invited)","display_name":"Wafer scale interconnect and pathfinding for machine learning hardware (invited)","publication_year":2020,"publication_date":"2020-11-05","ids":{"openalex":"https://openalex.org/W3111509700","doi":"https://doi.org/10.1145/3414622.3432992","mag":"3111509700"},"language":"en","primary_location":{"id":"doi:10.1145/3414622.3432992","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3414622.3432992","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the Workshop on System-Level Interconnect: Problems and Pathfinding Workshop","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5020251935","display_name":"Patrick Groeneveld","orcid":null},"institutions":[{"id":"https://openalex.org/I4401726927","display_name":"Cerebras Systems (United States)","ror":"https://ror.org/040zz8080","country_code":null,"type":"company","lineage":["https://openalex.org/I4401726927"]}],"countries":[],"is_corresponding":true,"raw_author_name":"Patrick Groeneveld","raw_affiliation_strings":["Cerebras Systems"],"affiliations":[{"raw_affiliation_string":"Cerebras Systems","institution_ids":["https://openalex.org/I4401726927"]}]}],"institutions":[],"countries_distinct_count":0,"institutions_distinct_count":1,"corresponding_author_ids":["https://openalex.org/A5020251935"],"corresponding_institution_ids":["https://openalex.org/I4401726927"],"apc_list":null,"apc_paid":null,"fwci":0.411,"has_fulltext":false,"cited_by_count":4,"citation_normalized_percentile":{"value":0.62348504,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"1"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T12808","display_name":"Ferroelectric and Negative Capacitance Devices","score":0.9919000267982483,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T12808","display_name":"Ferroelectric and Negative Capacitance Devices","score":0.9919000267982483,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9894000291824341,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9858999848365784,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7558039426803589},{"id":"https://openalex.org/keywords/speedup","display_name":"Speedup","score":0.7523524761199951},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.5462058782577515},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.5117406845092773},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.4990425109863281},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.4583965241909027},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.4465206563472748},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.4265744686126709},{"id":"https://openalex.org/keywords/scale","display_name":"Scale (ratio)","score":0.4242188632488251},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.396751344203949},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3457496166229248},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.09855514764785767},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.08089566230773926}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7558039426803589},{"id":"https://openalex.org/C68339613","wikidata":"https://www.wikidata.org/wiki/Q1549489","display_name":"Speedup","level":2,"score":0.7523524761199951},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.5462058782577515},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.5117406845092773},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.4990425109863281},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.4583965241909027},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4465206563472748},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.4265744686126709},{"id":"https://openalex.org/C2778755073","wikidata":"https://www.wikidata.org/wiki/Q10858537","display_name":"Scale (ratio)","level":2,"score":0.4242188632488251},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.396751344203949},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3457496166229248},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.09855514764785767},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.08089566230773926},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/3414622.3432992","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3414622.3432992","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the Workshop on System-Level Interconnect: Problems and Pathfinding Workshop","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W2058965144","https://openalex.org/W2164382479","https://openalex.org/W2146343568","https://openalex.org/W98480971","https://openalex.org/W2150291671","https://openalex.org/W2013643406","https://openalex.org/W2027972911","https://openalex.org/W2157978810","https://openalex.org/W2597809628","https://openalex.org/W2018755015"],"abstract_inverted_index":{"The":[0,15,93,124],"extreme":[1],"compute":[2,33,83,152,166,176],"requirements":[3],"of":[4,13,130,164],"Machine":[5],"Learning":[6],"(ML)":[7],"drives":[8],"an":[9],"entirely":[10],"new":[11],"generation":[12],"hardware.":[14],"very":[16,121],"compute-intensive":[17],"ML":[18,41,102,142],"training":[19,50,115,132],"is":[20,117,126],"generally":[21],"done":[22],"in":[23,110,119],"data":[24,51,116],"centers":[25],"using":[26],"re-purposed":[27],"GPUs.":[28],"This":[29],"provides":[30],"cost-efficient":[31],"floating-point":[32],"hardware":[34,111],"that":[35,78],"interfaces":[36],"with":[37,72,85],"the":[38,49,60,100,114,131,141,150,160,165,169,175],"well-known":[39],"TensorFlow":[40],"platform.":[42],"To":[43],"run":[44],"on":[45,149],"a":[46,68,73,89,127],"GPU,":[47],"however,":[48],"and":[52,64,147,168],"weights":[53,106],"needs":[54],"to":[55,58,107,172],"be":[56],"segmented":[57],"fit":[59],"limited":[61],"on-chip":[62],"memory":[63],"bandwidth.":[65],"Cerebras":[66],"takes":[67],"radically":[69],"different":[70],"approach":[71],"massive":[74,94],"22x22cm":[75],"monolithic":[76],"chip":[77],"contains":[79],"over":[80],"400,000":[81],"powerful":[82],"cores":[84],"1.2":[86],"Trillion":[87],"(with":[88],"T)":[90],"transistors":[91],"[1].":[92],"Wafer":[95],"Scale":[96],"Engine":[97],"(WSE)":[98],"allows":[99],"entire":[101],"model":[103],"including":[104],"all":[105],"remain":[108],"stationary":[109],"while":[112],"only":[113],"streamed":[118],"at":[120],"high":[122],"speed.":[123],"result":[125],"dramatic":[128],"speedup":[129],"process.":[133],"In":[134,154],"this":[135],"presentation":[136],"we":[137,157],"will":[138,158],"address":[139,159],"how":[140],"kernels":[143],"are":[144],"synthesized,":[145],"placed":[146],"routed":[148],"WSE":[151],"fabric.":[153],"more":[155],"detail":[156],"unique":[161],"interconnect":[162],"properties":[163],"fabric,":[167],"EDA-inspired":[170],"solutions":[171],"efficiently":[173],"map":[174],"kernels.":[177]},"counts_by_year":[{"year":2023,"cited_by_count":1},{"year":2021,"cited_by_count":3}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}