{"id":"https://openalex.org/W3159428183","doi":"https://doi.org/10.1145/3412841.3441928","title":"Automating the design flow under dynamic partial reconfiguration for hardware-software co-design in FPGA SoC","display_name":"Automating the design flow under dynamic partial reconfiguration for hardware-software co-design in FPGA SoC","publication_year":2021,"publication_date":"2021-03-22","ids":{"openalex":"https://openalex.org/W3159428183","doi":"https://doi.org/10.1145/3412841.3441928","mag":"3159428183"},"language":"en","primary_location":{"id":"doi:10.1145/3412841.3441928","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3412841.3441928","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 36th Annual ACM Symposium on Applied Computing","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"green","oa_url":"http://hdl.handle.net/11382/538331","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5042344201","display_name":"Biruk Seyoum","orcid":"https://orcid.org/0000-0001-5399-2590"},"institutions":[],"countries":[],"is_corresponding":true,"raw_author_name":"Biruk Seyoum","raw_affiliation_strings":["TeCIP Institute, Scuola, Pisa, Italy"],"affiliations":[{"raw_affiliation_string":"TeCIP Institute, Scuola, Pisa, Italy","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5067225488","display_name":"Marco Pagani","orcid":"https://orcid.org/0000-0003-2321-6659"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Marco Pagani","raw_affiliation_strings":["TeCIP Institute, Scuola, Pisa, Italy"],"affiliations":[{"raw_affiliation_string":"TeCIP Institute, Scuola, Pisa, Italy","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5072482410","display_name":"Alessandro Biondi","orcid":"https://orcid.org/0000-0002-6625-9336"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Alessandro Biondi","raw_affiliation_strings":["TeCIP Institute, Scuola, Pisa, Italy"],"affiliations":[{"raw_affiliation_string":"TeCIP Institute, Scuola, Pisa, Italy","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5024920325","display_name":"Giorgio Buttazzo","orcid":"https://orcid.org/0000-0003-4959-4017"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Giorgio Buttazzo","raw_affiliation_strings":["TeCIP Institute, Scuola, Pisa, Italy"],"affiliations":[{"raw_affiliation_string":"TeCIP Institute, Scuola, Pisa, Italy","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":0,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5042344201"],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":1.8784,"has_fulltext":false,"cited_by_count":9,"citation_normalized_percentile":{"value":0.84851287,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":null,"issue":null,"first_page":"481","last_page":"490"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/control-reconfiguration","display_name":"Control reconfiguration","score":0.9394380450248718},{"id":"https://openalex.org/keywords/design-flow","display_name":"Design flow","score":0.8415482044219971},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.7338284850120544},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7080602049827576},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.6823172569274902},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.5096237659454346},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4970300495624542},{"id":"https://openalex.org/keywords/software-design","display_name":"Software design","score":0.47304290533065796},{"id":"https://openalex.org/keywords/engineering-design-process","display_name":"Engineering design process","score":0.4222240447998047},{"id":"https://openalex.org/keywords/design-process","display_name":"Design process","score":0.41923320293426514},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3469478487968445},{"id":"https://openalex.org/keywords/software-development","display_name":"Software development","score":0.18067699670791626},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.1663937270641327},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.16190996766090393},{"id":"https://openalex.org/keywords/work-in-process","display_name":"Work in process","score":0.0677827000617981}],"concepts":[{"id":"https://openalex.org/C119701452","wikidata":"https://www.wikidata.org/wiki/Q5165881","display_name":"Control reconfiguration","level":2,"score":0.9394380450248718},{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.8415482044219971},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.7338284850120544},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7080602049827576},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6823172569274902},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.5096237659454346},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4970300495624542},{"id":"https://openalex.org/C52913732","wikidata":"https://www.wikidata.org/wiki/Q857102","display_name":"Software design","level":4,"score":0.47304290533065796},{"id":"https://openalex.org/C34972735","wikidata":"https://www.wikidata.org/wiki/Q2920267","display_name":"Engineering design process","level":2,"score":0.4222240447998047},{"id":"https://openalex.org/C48262172","wikidata":"https://www.wikidata.org/wiki/Q16908765","display_name":"Design process","level":3,"score":0.41923320293426514},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3469478487968445},{"id":"https://openalex.org/C529173508","wikidata":"https://www.wikidata.org/wiki/Q638608","display_name":"Software development","level":3,"score":0.18067699670791626},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.1663937270641327},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.16190996766090393},{"id":"https://openalex.org/C174998907","wikidata":"https://www.wikidata.org/wiki/Q357662","display_name":"Work in process","level":2,"score":0.0677827000617981},{"id":"https://openalex.org/C21547014","wikidata":"https://www.wikidata.org/wiki/Q1423657","display_name":"Operations management","level":1,"score":0.0},{"id":"https://openalex.org/C78519656","wikidata":"https://www.wikidata.org/wiki/Q101333","display_name":"Mechanical engineering","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1145/3412841.3441928","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3412841.3441928","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 36th Annual ACM Symposium on Applied Computing","raw_type":"proceedings-article"},{"id":"pmh:oai:www.iris.sssup.it:11382/538331","is_oa":true,"landing_page_url":"http://hdl.handle.net/11382/538331","pdf_url":null,"source":{"id":"https://openalex.org/S4377196376","display_name":"CINECA IRIS Institutional Research Information System (Sant'Anna School of Advanced Studies)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I162290304","host_organization_name":"Scuola Superiore Sant'Anna","host_organization_lineage":["https://openalex.org/I162290304"],"host_organization_lineage_names":[],"type":"repository"},"license":"other-oa","license_id":"https://openalex.org/licenses/other-oa","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"info:eu-repo/semantics/conferenceObject"}],"best_oa_location":{"id":"pmh:oai:www.iris.sssup.it:11382/538331","is_oa":true,"landing_page_url":"http://hdl.handle.net/11382/538331","pdf_url":null,"source":{"id":"https://openalex.org/S4377196376","display_name":"CINECA IRIS Institutional Research Information System (Sant'Anna School of Advanced Studies)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I162290304","host_organization_name":"Scuola Superiore Sant'Anna","host_organization_lineage":["https://openalex.org/I162290304"],"host_organization_lineage_names":[],"type":"repository"},"license":"other-oa","license_id":"https://openalex.org/licenses/other-oa","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"info:eu-repo/semantics/conferenceObject"},"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","score":0.5099999904632568,"id":"https://metadata.un.org/sdg/9"}],"awards":[{"id":"https://openalex.org/G5759401209","display_name":null,"funder_award_id":"871669","funder_id":"https://openalex.org/F4320332999","funder_display_name":"Horizon 2020 Framework Programme"},{"id":"https://openalex.org/G7331901853","display_name":null,"funder_award_id":"EU H2020","funder_id":"https://openalex.org/F4320332999","funder_display_name":"Horizon 2020 Framework Programme"}],"funders":[{"id":"https://openalex.org/F4320332999","display_name":"Horizon 2020 Framework Programme","ror":"https://ror.org/00k4n6c32"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":19,"referenced_works":["https://openalex.org/W92551552","https://openalex.org/W165160209","https://openalex.org/W1503401752","https://openalex.org/W1621597718","https://openalex.org/W1632220086","https://openalex.org/W1975516330","https://openalex.org/W1986871373","https://openalex.org/W2118073772","https://openalex.org/W2183064252","https://openalex.org/W2268762552","https://openalex.org/W2399857432","https://openalex.org/W2511789865","https://openalex.org/W2565125333","https://openalex.org/W2570914145","https://openalex.org/W2588101650","https://openalex.org/W2759981985","https://openalex.org/W2913355112","https://openalex.org/W2979970871","https://openalex.org/W3102169921"],"related_works":["https://openalex.org/W1521892965","https://openalex.org/W2016688446","https://openalex.org/W2586089541","https://openalex.org/W1977754481","https://openalex.org/W135171136","https://openalex.org/W2148601120","https://openalex.org/W2101430679","https://openalex.org/W336145253","https://openalex.org/W2381555396","https://openalex.org/W2029812558"],"abstract_inverted_index":{"Despite":[0],"its":[1],"benefits,":[2],"hardware":[3,79],"acceleration":[4],"under":[5],"dynamic":[6],"partial":[7],"reconfiguration":[8,96],"(DPR)":[9],"has":[10],"not":[11],"been":[12],"fully":[13],"leveraged":[14],"by":[15],"many":[16],"system":[17],"designers,":[18],"mostly":[19],"due":[20],"to":[21,36,68],"the":[22,25,30,38,53,57,72,76,82,88,91,95],"complexities":[23],"of":[24,32,75,81,87,90],"DPR":[26,59],"design":[27,34,39,45,60,64],"flow":[28,61],"and":[29,78],"lack":[31],"efficient":[33],"tools":[35],"automate":[37],"process.":[40],"Furthermore,":[41],"making":[42],"such":[43],"a":[44],"approach":[46],"suitable":[47],"for":[48,55,71],"real-time":[49],"embedded":[50],"systems":[51],"requires":[52],"need":[54],"extending":[56],"standard":[58],"with":[62],"additional":[63],"steps,":[65],"which":[66],"have":[67],"accurately":[69],"account":[70],"timing":[73],"behavior":[74],"software":[77],"components":[80,89],"design,":[83],"as":[84,86],"well":[85],"computing":[92],"platform":[93],"(e.g.,":[94],"interface).":[97]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2024,"cited_by_count":1},{"year":2023,"cited_by_count":4},{"year":2022,"cited_by_count":1},{"year":2021,"cited_by_count":2}],"updated_date":"2026-03-13T16:22:10.518609","created_date":"2025-10-10T00:00:00"}
