{"id":"https://openalex.org/W3113194127","doi":"https://doi.org/10.1145/3400302.3415628","title":"Power distribution network generation for optimizing IR-drop aware timing","display_name":"Power distribution network generation for optimizing IR-drop aware timing","publication_year":2020,"publication_date":"2020-11-02","ids":{"openalex":"https://openalex.org/W3113194127","doi":"https://doi.org/10.1145/3400302.3415628","mag":"3113194127"},"language":"en","primary_location":{"id":"doi:10.1145/3400302.3415628","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3400302.3415628","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 39th International Conference on Computer-Aided Design","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5012114201","display_name":"Wen-Hsiang Chang","orcid":"https://orcid.org/0000-0001-5851-1848"},"institutions":[{"id":"https://openalex.org/I148366613","display_name":"National Yang Ming Chiao Tung University","ror":"https://ror.org/00se2k293","country_code":"TW","type":"education","lineage":["https://openalex.org/I148366613"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Wen-Hsiang Chang","raw_affiliation_strings":["National Chiao Tung University, Hsinchu, Taiwan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"National Chiao Tung University, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I148366613"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5000216467","display_name":"Li-Yi Lin","orcid":null},"institutions":[{"id":"https://openalex.org/I901624438","display_name":"Realtek (Taiwan)","ror":"https://ror.org/05x1ffr83","country_code":"TW","type":"company","lineage":["https://openalex.org/I901624438"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Li-Yi Lin","raw_affiliation_strings":["Realtek Semiconductor Corp., Hsinchu, Taiwan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Realtek Semiconductor Corp., Hsinchu, Taiwan","institution_ids":["https://openalex.org/I901624438"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5011277985","display_name":"Yuguang Chen","orcid":"https://orcid.org/0000-0003-4520-5395"},"institutions":[{"id":"https://openalex.org/I22265921","display_name":"National Central University","ror":"https://ror.org/00944ve71","country_code":"TW","type":"education","lineage":["https://openalex.org/I22265921"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Yu-Guang Chen","raw_affiliation_strings":["National Central University, Taoyuan, Taiwan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"National Central University, Taoyuan, Taiwan","institution_ids":["https://openalex.org/I22265921"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5045156360","display_name":"Mango C.-T. Chao","orcid":"https://orcid.org/0000-0002-7299-9015"},"institutions":[{"id":"https://openalex.org/I148366613","display_name":"National Yang Ming Chiao Tung University","ror":"https://ror.org/00se2k293","country_code":"TW","type":"education","lineage":["https://openalex.org/I148366613"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Mango C.-T. Chao","raw_affiliation_strings":["National Chiao Tung University, Hsinchu, Taiwan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"National Chiao Tung University, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I148366613"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.1041,"has_fulltext":false,"cited_by_count":6,"citation_normalized_percentile":{"value":0.45913739,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":97},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"9"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11444","display_name":"Electromagnetic Compatibility and Noise Suppression","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/power-network-design","display_name":"Power network design","score":0.8417980670928955},{"id":"https://openalex.org/keywords/static-timing-analysis","display_name":"Static timing analysis","score":0.7205021381378174},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6322615146636963},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.5727883577346802},{"id":"https://openalex.org/keywords/overhead","display_name":"Overhead (engineering)","score":0.5592049360275269},{"id":"https://openalex.org/keywords/macro","display_name":"Macro","score":0.5243939757347107},{"id":"https://openalex.org/keywords/voltage-drop","display_name":"Voltage drop","score":0.5193975567817688},{"id":"https://openalex.org/keywords/process-corners","display_name":"Process corners","score":0.5186647176742554},{"id":"https://openalex.org/keywords/drop","display_name":"Drop (telecommunication)","score":0.517368733882904},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.45798033475875854},{"id":"https://openalex.org/keywords/physical-design","display_name":"Physical design","score":0.45426055788993835},{"id":"https://openalex.org/keywords/dynamic-voltage-scaling","display_name":"Dynamic voltage scaling","score":0.43362003564834595},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.43355563282966614},{"id":"https://openalex.org/keywords/integrated-circuit-design","display_name":"Integrated circuit design","score":0.42606738209724426},{"id":"https://openalex.org/keywords/placement","display_name":"Placement","score":0.416718989610672},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.40791234374046326},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.38898766040802},{"id":"https://openalex.org/keywords/circuit-design","display_name":"Circuit design","score":0.3363323211669922},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.21595355868339539},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2098059356212616}],"concepts":[{"id":"https://openalex.org/C164565468","wikidata":"https://www.wikidata.org/wiki/Q7236535","display_name":"Power network design","level":3,"score":0.8417980670928955},{"id":"https://openalex.org/C93682380","wikidata":"https://www.wikidata.org/wiki/Q2025226","display_name":"Static timing analysis","level":2,"score":0.7205021381378174},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6322615146636963},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.5727883577346802},{"id":"https://openalex.org/C2779960059","wikidata":"https://www.wikidata.org/wiki/Q7113681","display_name":"Overhead (engineering)","level":2,"score":0.5592049360275269},{"id":"https://openalex.org/C166955791","wikidata":"https://www.wikidata.org/wiki/Q629579","display_name":"Macro","level":2,"score":0.5243939757347107},{"id":"https://openalex.org/C82178898","wikidata":"https://www.wikidata.org/wiki/Q166839","display_name":"Voltage drop","level":3,"score":0.5193975567817688},{"id":"https://openalex.org/C192615534","wikidata":"https://www.wikidata.org/wiki/Q7247268","display_name":"Process corners","level":3,"score":0.5186647176742554},{"id":"https://openalex.org/C2781345722","wikidata":"https://www.wikidata.org/wiki/Q5308388","display_name":"Drop (telecommunication)","level":2,"score":0.517368733882904},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.45798033475875854},{"id":"https://openalex.org/C188817802","wikidata":"https://www.wikidata.org/wiki/Q13426855","display_name":"Physical design","level":3,"score":0.45426055788993835},{"id":"https://openalex.org/C2776047111","wikidata":"https://www.wikidata.org/wiki/Q632037","display_name":"Dynamic voltage scaling","level":3,"score":0.43362003564834595},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.43355563282966614},{"id":"https://openalex.org/C74524168","wikidata":"https://www.wikidata.org/wiki/Q1074539","display_name":"Integrated circuit design","level":2,"score":0.42606738209724426},{"id":"https://openalex.org/C117690923","wikidata":"https://www.wikidata.org/wiki/Q1484784","display_name":"Placement","level":4,"score":0.416718989610672},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.40791234374046326},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.38898766040802},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.3363323211669922},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.21595355868339539},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2098059356212616},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/3400302.3415628","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3400302.3415628","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 39th International Conference on Computer-Aided Design","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure","score":0.46000000834465027}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":25,"referenced_works":["https://openalex.org/W2053008534","https://openalex.org/W2053737126","https://openalex.org/W2089703610","https://openalex.org/W2096235237","https://openalex.org/W2100032953","https://openalex.org/W2100150136","https://openalex.org/W2101029991","https://openalex.org/W2101512735","https://openalex.org/W2105302023","https://openalex.org/W2106006800","https://openalex.org/W2112333925","https://openalex.org/W2118410973","https://openalex.org/W2129764097","https://openalex.org/W2130464226","https://openalex.org/W2131254145","https://openalex.org/W2138263555","https://openalex.org/W2144774282","https://openalex.org/W2152850399","https://openalex.org/W2158728973","https://openalex.org/W2527193322","https://openalex.org/W2607159714","https://openalex.org/W2900150243","https://openalex.org/W4229487452","https://openalex.org/W4236504040","https://openalex.org/W4239027469"],"related_works":["https://openalex.org/W2132496963","https://openalex.org/W3144161597","https://openalex.org/W2121845874","https://openalex.org/W2169671942","https://openalex.org/W1974474301","https://openalex.org/W1582620393","https://openalex.org/W2135304146","https://openalex.org/W4231811236","https://openalex.org/W4386523879","https://openalex.org/W3113194127"],"abstract_inverted_index":{"As":[0],"supply":[1],"voltage":[2,30],"keeps":[3],"scaling,":[4],"the":[5,14,35,44,53,61,112,136],"timing":[6,24,57,63,69,75,93,120],"of":[7,16,64,114,138],"an":[8,129],"IC":[9],"becomes":[10],"more":[11],"sensitive":[12],"to":[13,31,41,110,127,176],"IR-drop":[15,67,91,118],"its":[17],"power":[18,139],"distribution":[19],"network":[20],"(PDN).":[21],"In":[22],"conventional":[23],"signoff,":[25],"designers":[26],"assign":[27],"a":[28,65,80,86,96,115,122,159,177],"fixed":[29],"all":[32,188,193],"cells":[33,49],"during":[34],"entire":[36],"analysis":[37,70],"process,":[38],"which":[39],"leads":[40],"over-design":[42],"since":[43],"exact":[45],"voltages":[46],"at":[47],"most":[48],"are":[50],"larger":[51],"than":[52],"assigned":[54],"value":[55],"for":[56,74,89],"analysis.":[58],"To":[59],"reflect":[60],"actual":[62],"circuit,":[66],"aware":[68,92,119],"should":[71],"be":[72,203],"applied":[73],"signoff.":[76],"This":[77],"paper":[78],"proposes":[79],"framework":[81,104,155,186],"that":[82,153],"can":[83,156,202],"automatically":[84],"generate":[85,158],"refined":[87],"PDN":[88,99,116,132,160,194],"optimizing":[90],"based":[94,125,146],"on":[95,117,147,181],"given":[97],"initial":[98],"and":[100,121,171,191,200],"cell":[101],"placement.":[102],"Our":[103,185],"uses":[105],"two":[106],"novel":[107,123],"timing-cost":[108],"indexes":[109],"measure":[111],"impact":[113],"dynamic-programming":[124],"algorithm":[126],"obtain":[128],"optimal":[130],"timing-driven":[131],"while":[133],"efficiently":[134],"handling":[135],"discontinuity":[137],"rails":[140],"caused":[141],"by":[142],"macros.":[143],"The":[144],"experiments":[145],"various":[148],"28nm":[149],"industrial":[150,207],"designs":[151],"demonstrate":[152],"our":[154],"always":[157],"resulting":[161],"in":[162],"less":[163,167,172],"worst-case":[164],"negative":[165,169],"slack,":[166,170],"total":[168],"timing-violating":[173],"paths,":[174],"compared":[175],"previous":[178],"work":[179],"focusing":[180],"minimizing":[182],"routing":[183],"overhead.":[184],"accesses":[187],"design":[189,208],"information":[190],"makes":[192],"changes":[195],"through":[196],"commercial":[197],"EDA":[198],"tools,":[199],"hence":[201],"easily":[204],"integrated":[205],"into":[206],"flows.":[209]},"counts_by_year":[{"year":2025,"cited_by_count":2},{"year":2024,"cited_by_count":3},{"year":2023,"cited_by_count":1}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}
