{"id":"https://openalex.org/W3128763347","doi":"https://doi.org/10.1145/3394885.3431543","title":"A Robust Batch Bayesian Optimization for Analog Circuit Synthesis via Local Penalization","display_name":"A Robust Batch Bayesian Optimization for Analog Circuit Synthesis via Local Penalization","publication_year":2021,"publication_date":"2021-01-18","ids":{"openalex":"https://openalex.org/W3128763347","doi":"https://doi.org/10.1145/3394885.3431543","mag":"3128763347"},"language":"en","primary_location":{"id":"doi:10.1145/3394885.3431543","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3394885.3431543","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 26th Asia and South Pacific Design Automation Conference","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5082912188","display_name":"Jiangli Huang","orcid":"https://orcid.org/0000-0001-9111-8474"},"institutions":[{"id":"https://openalex.org/I4210132426","display_name":"Shanghai Fudan Microelectronics (China)","ror":"https://ror.org/02vfj3j86","country_code":"CN","type":"company","lineage":["https://openalex.org/I4210132426"]},{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":true,"raw_author_name":"Jiangli Huang","raw_affiliation_strings":["State Key Lab of ASIC System, School of Microelectronics, Fudan University, China"],"affiliations":[{"raw_affiliation_string":"State Key Lab of ASIC System, School of Microelectronics, Fudan University, China","institution_ids":["https://openalex.org/I4210132426","https://openalex.org/I24943067"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5045464812","display_name":"Fan Yang","orcid":"https://orcid.org/0000-0003-2164-8175"},"institutions":[{"id":"https://openalex.org/I4210132426","display_name":"Shanghai Fudan Microelectronics (China)","ror":"https://ror.org/02vfj3j86","country_code":"CN","type":"company","lineage":["https://openalex.org/I4210132426"]},{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Fan Yang","raw_affiliation_strings":["State Key Lab of ASIC System, School of Microelectronics, Fudan University, China"],"affiliations":[{"raw_affiliation_string":"State Key Lab of ASIC System, School of Microelectronics, Fudan University, China","institution_ids":["https://openalex.org/I4210132426","https://openalex.org/I24943067"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5037328458","display_name":"Changhao Yan","orcid":"https://orcid.org/0000-0002-8936-3945"},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]},{"id":"https://openalex.org/I4210132426","display_name":"Shanghai Fudan Microelectronics (China)","ror":"https://ror.org/02vfj3j86","country_code":"CN","type":"company","lineage":["https://openalex.org/I4210132426"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Changhao Yan","raw_affiliation_strings":["State Key Lab of ASIC System, School of Microelectronics, Fudan University, China"],"affiliations":[{"raw_affiliation_string":"State Key Lab of ASIC System, School of Microelectronics, Fudan University, China","institution_ids":["https://openalex.org/I4210132426","https://openalex.org/I24943067"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5054960059","display_name":"Dian Zhou","orcid":"https://orcid.org/0000-0002-2648-5232"},"institutions":[{"id":"https://openalex.org/I162577319","display_name":"The University of Texas at Dallas","ror":"https://ror.org/049emcs32","country_code":"US","type":"education","lineage":["https://openalex.org/I162577319"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Dian Zhou","raw_affiliation_strings":["Department of Electrical Engineering, University of Texas at Dallas, Richardson, TX, U.S.A"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, University of Texas at Dallas, Richardson, TX, U.S.A","institution_ids":["https://openalex.org/I162577319"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5064213921","display_name":"Xuan Zeng","orcid":"https://orcid.org/0000-0002-8097-4053"},"institutions":[{"id":"https://openalex.org/I4210132426","display_name":"Shanghai Fudan Microelectronics (China)","ror":"https://ror.org/02vfj3j86","country_code":"CN","type":"company","lineage":["https://openalex.org/I4210132426"]},{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Xuan Zeng","raw_affiliation_strings":["State Key Lab of ASIC System, School of Microelectronics, Fudan University, China"],"affiliations":[{"raw_affiliation_string":"State Key Lab of ASIC System, School of Microelectronics, Fudan University, China","institution_ids":["https://openalex.org/I4210132426","https://openalex.org/I24943067"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5082912188"],"corresponding_institution_ids":["https://openalex.org/I24943067","https://openalex.org/I4210132426"],"apc_list":null,"apc_paid":null,"fwci":0.2959,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.57966925,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":95},"biblio":{"volume":null,"issue":null,"first_page":"146","last_page":"151"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10848","display_name":"Advanced Multi-Objective Optimization Algorithms","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10848","display_name":"Advanced Multi-Objective Optimization Algorithms","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9973999857902527,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/bayesian-optimization","display_name":"Bayesian optimization","score":0.7833641767501831},{"id":"https://openalex.org/keywords/robustness","display_name":"Robustness (evolution)","score":0.7527568340301514},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6347949504852295},{"id":"https://openalex.org/keywords/bayesian-probability","display_name":"Bayesian probability","score":0.6109087467193604},{"id":"https://openalex.org/keywords/convergence","display_name":"Convergence (economics)","score":0.5685058832168579},{"id":"https://openalex.org/keywords/mathematical-optimization","display_name":"Mathematical optimization","score":0.4774492383003235},{"id":"https://openalex.org/keywords/analogue-electronics","display_name":"Analogue electronics","score":0.4663699269294739},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.37150484323501587},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.35111355781555176},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.237665593624115},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.23679518699645996},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.10229074954986572}],"concepts":[{"id":"https://openalex.org/C2778049539","wikidata":"https://www.wikidata.org/wiki/Q17002908","display_name":"Bayesian optimization","level":2,"score":0.7833641767501831},{"id":"https://openalex.org/C63479239","wikidata":"https://www.wikidata.org/wiki/Q7353546","display_name":"Robustness (evolution)","level":3,"score":0.7527568340301514},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6347949504852295},{"id":"https://openalex.org/C107673813","wikidata":"https://www.wikidata.org/wiki/Q812534","display_name":"Bayesian probability","level":2,"score":0.6109087467193604},{"id":"https://openalex.org/C2777303404","wikidata":"https://www.wikidata.org/wiki/Q759757","display_name":"Convergence (economics)","level":2,"score":0.5685058832168579},{"id":"https://openalex.org/C126255220","wikidata":"https://www.wikidata.org/wiki/Q141495","display_name":"Mathematical optimization","level":1,"score":0.4774492383003235},{"id":"https://openalex.org/C29074008","wikidata":"https://www.wikidata.org/wiki/Q174925","display_name":"Analogue electronics","level":3,"score":0.4663699269294739},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.37150484323501587},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.35111355781555176},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.237665593624115},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.23679518699645996},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.10229074954986572},{"id":"https://openalex.org/C104317684","wikidata":"https://www.wikidata.org/wiki/Q7187","display_name":"Gene","level":2,"score":0.0},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0},{"id":"https://openalex.org/C185592680","wikidata":"https://www.wikidata.org/wiki/Q2329","display_name":"Chemistry","level":0,"score":0.0},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.0},{"id":"https://openalex.org/C50522688","wikidata":"https://www.wikidata.org/wiki/Q189833","display_name":"Economic growth","level":1,"score":0.0},{"id":"https://openalex.org/C55493867","wikidata":"https://www.wikidata.org/wiki/Q7094","display_name":"Biochemistry","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/3394885.3431543","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3394885.3431543","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 26th Asia and South Pacific Design Automation Conference","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":26,"referenced_works":["https://openalex.org/W61667912","https://openalex.org/W1510052597","https://openalex.org/W1665719966","https://openalex.org/W1964239621","https://openalex.org/W1998752433","https://openalex.org/W2065183815","https://openalex.org/W2144133630","https://openalex.org/W2147059000","https://openalex.org/W2155811837","https://openalex.org/W2161359911","https://openalex.org/W2168148636","https://openalex.org/W2171048418","https://openalex.org/W2192203593","https://openalex.org/W2409689189","https://openalex.org/W2526264695","https://openalex.org/W2616619952","https://openalex.org/W2769791151","https://openalex.org/W2772124661","https://openalex.org/W2772152190","https://openalex.org/W2804987245","https://openalex.org/W2964136676","https://openalex.org/W3100083105","https://openalex.org/W3102150134","https://openalex.org/W4211049957","https://openalex.org/W4253246357","https://openalex.org/W6666609154"],"related_works":["https://openalex.org/W3106461837","https://openalex.org/W4364381099","https://openalex.org/W3168182983","https://openalex.org/W4321472004","https://openalex.org/W4387079005","https://openalex.org/W4283700523","https://openalex.org/W2968265130","https://openalex.org/W4221166418","https://openalex.org/W2973085194","https://openalex.org/W2375192119"],"abstract_inverted_index":{"Bayesian":[0,20,47,62],"optimization":[1,21,48],"has":[2,22],"been":[3,23],"successfully":[4],"introduced":[5],"to":[6,25,39,75,117,123],"analog":[7,67,144],"circuit":[8,31,68],"synthesis":[9],"recently.":[10],"Since":[11],"the":[12,36,40,77,89,120,125,138,151,156],"evaluations":[13],"of":[14,88,127,155],"performances":[15],"are":[16],"computational":[17],"expensive,":[18],"batch":[19],"proposed":[24,129,133,157],"run":[26],"simulations":[27,32],"in":[28,83],"parallel.":[29],"However,":[30],"may":[33,50],"fail":[34],"during":[35],"optimization,":[37],"due":[38],"improper":[41],"design":[42],"variables.":[43],"In":[44,54],"such":[45],"cases,":[46],"methods":[49],"have":[51,149],"poor":[52],"performance.":[53],"this":[55],"paper,":[56],"we":[57,109],"propose":[58,110],"a":[59],"Robust":[60],"Batch":[61],"Optimization":[63],"approach":[64,134],"(RBBO)":[65],"for":[66],"synthesis.":[69],"Local":[70,113],"penalization":[71],"(LP)":[72],"is":[73,135],"used":[74],"capture":[76],"local":[78],"repulsion":[79],"between":[80],"query":[81,90],"points":[82,91,98],"one":[84],"batch.":[85],"The":[86,96,132,146],"diversity":[87],"can":[92,102],"thus":[93],"be":[94,104],"guaranteed.":[95],"failed":[97],"and":[99,153],"their":[100],"neighborhoods":[101],"also":[103],"excluded":[105],"by":[106],"LP.":[107],"Moreover,":[108],"an":[111],"Adaptive":[112],"Penalization":[114],"(ALP)":[115],"strategy":[116],"adaptively":[118],"scale":[119],"penalized":[121],"areas":[122],"improve":[124],"convergence":[126],"our":[128],"RBBO":[130],"method.":[131,158],"compared":[136],"with":[137,141],"state-of-the-art":[139],"algorithms":[140],"several":[142],"practical":[143],"circuits.":[145],"experimental":[147],"results":[148],"demonstrated":[150],"efficiency":[152],"robustness":[154]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2024,"cited_by_count":1},{"year":2023,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}