{"id":"https://openalex.org/W3127689019","doi":"https://doi.org/10.1145/3394885.3431414","title":"Combining Memory Partitioning and Subtask Generation for Parallel Data Access on CGRAs","display_name":"Combining Memory Partitioning and Subtask Generation for Parallel Data Access on CGRAs","publication_year":2021,"publication_date":"2021-01-18","ids":{"openalex":"https://openalex.org/W3127689019","doi":"https://doi.org/10.1145/3394885.3431414","mag":"3127689019"},"language":"en","primary_location":{"id":"doi:10.1145/3394885.3431414","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3394885.3431414","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 26th Asia and South Pacific Design Automation Conference","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5100354274","display_name":"Cheng Li","orcid":"https://orcid.org/0000-0002-8711-8970"},"institutions":[{"id":"https://openalex.org/I4210119392","display_name":"Institute of Microelectronics","ror":"https://ror.org/02s6gs133","country_code":"CN","type":"facility","lineage":["https://openalex.org/I19820366","https://openalex.org/I4210119392"]},{"id":"https://openalex.org/I99065089","display_name":"Tsinghua University","ror":"https://ror.org/03cve4549","country_code":"CN","type":"education","lineage":["https://openalex.org/I99065089"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Cheng Li","raw_affiliation_strings":["Institute of Microelectronics, Tsinghua University, Beijing, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Institute of Microelectronics, Tsinghua University, Beijing, China","institution_ids":["https://openalex.org/I99065089","https://openalex.org/I4210119392"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5022808670","display_name":"Jiangyuan Gu","orcid":"https://orcid.org/0000-0003-1190-7524"},"institutions":[{"id":"https://openalex.org/I4210119392","display_name":"Institute of Microelectronics","ror":"https://ror.org/02s6gs133","country_code":"CN","type":"facility","lineage":["https://openalex.org/I19820366","https://openalex.org/I4210119392"]},{"id":"https://openalex.org/I99065089","display_name":"Tsinghua University","ror":"https://ror.org/03cve4549","country_code":"CN","type":"education","lineage":["https://openalex.org/I99065089"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Jiangyuan Gu","raw_affiliation_strings":["Institute of Microelectronics, Tsinghua University, Beijing, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Institute of Microelectronics, Tsinghua University, Beijing, China","institution_ids":["https://openalex.org/I99065089","https://openalex.org/I4210119392"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5054524841","display_name":"Shouyi Yin","orcid":"https://orcid.org/0000-0003-2309-572X"},"institutions":[{"id":"https://openalex.org/I4210119392","display_name":"Institute of Microelectronics","ror":"https://ror.org/02s6gs133","country_code":"CN","type":"facility","lineage":["https://openalex.org/I19820366","https://openalex.org/I4210119392"]},{"id":"https://openalex.org/I99065089","display_name":"Tsinghua University","ror":"https://ror.org/03cve4549","country_code":"CN","type":"education","lineage":["https://openalex.org/I99065089"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Shouyi Yin","raw_affiliation_strings":["Institute of Microelectronics, Tsinghua University, Beijing, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Institute of Microelectronics, Tsinghua University, Beijing, China","institution_ids":["https://openalex.org/I99065089","https://openalex.org/I4210119392"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100358856","display_name":"Leibo Liu","orcid":"https://orcid.org/0000-0001-7548-4116"},"institutions":[{"id":"https://openalex.org/I4210119392","display_name":"Institute of Microelectronics","ror":"https://ror.org/02s6gs133","country_code":"CN","type":"facility","lineage":["https://openalex.org/I19820366","https://openalex.org/I4210119392"]},{"id":"https://openalex.org/I99065089","display_name":"Tsinghua University","ror":"https://ror.org/03cve4549","country_code":"CN","type":"education","lineage":["https://openalex.org/I99065089"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Leibo Liu","raw_affiliation_strings":["Institute of Microelectronics, Tsinghua University, Beijing, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Institute of Microelectronics, Tsinghua University, Beijing, China","institution_ids":["https://openalex.org/I99065089","https://openalex.org/I4210119392"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5036023084","display_name":"Shaojun Wei","orcid":"https://orcid.org/0000-0001-5117-7920"},"institutions":[{"id":"https://openalex.org/I4210119392","display_name":"Institute of Microelectronics","ror":"https://ror.org/02s6gs133","country_code":"CN","type":"facility","lineage":["https://openalex.org/I19820366","https://openalex.org/I4210119392"]},{"id":"https://openalex.org/I99065089","display_name":"Tsinghua University","ror":"https://ror.org/03cve4549","country_code":"CN","type":"education","lineage":["https://openalex.org/I99065089"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Shaojun Wei","raw_affiliation_strings":["Institute of Microelectronics, Tsinghua University, Beijing, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Institute of Microelectronics, Tsinghua University, Beijing, China","institution_ids":["https://openalex.org/I99065089","https://openalex.org/I4210119392"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"204","last_page":"209"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8758726119995117},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.7080401182174683},{"id":"https://openalex.org/keywords/memory-bandwidth","display_name":"Memory bandwidth","score":0.544714093208313},{"id":"https://openalex.org/keywords/uniform-memory-access","display_name":"Uniform memory access","score":0.5242079496383667},{"id":"https://openalex.org/keywords/data-access","display_name":"Data access","score":0.5178154110908508},{"id":"https://openalex.org/keywords/auxiliary-memory","display_name":"Auxiliary memory","score":0.5146340131759644},{"id":"https://openalex.org/keywords/kernel","display_name":"Kernel (algebra)","score":0.5079243779182434},{"id":"https://openalex.org/keywords/memory-management","display_name":"Memory management","score":0.501929759979248},{"id":"https://openalex.org/keywords/interleaved-memory","display_name":"Interleaved memory","score":0.47585341334342957},{"id":"https://openalex.org/keywords/exploit","display_name":"Exploit","score":0.45104432106018066},{"id":"https://openalex.org/keywords/computation","display_name":"Computation","score":0.41925686597824097},{"id":"https://openalex.org/keywords/performance-improvement","display_name":"Performance improvement","score":0.41925132274627686},{"id":"https://openalex.org/keywords/distributed-memory","display_name":"Distributed memory","score":0.41776710748672485},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.39035171270370483},{"id":"https://openalex.org/keywords/shared-memory","display_name":"Shared memory","score":0.39014336466789246},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.21616727113723755},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.17198070883750916},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.09838467836380005}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8758726119995117},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.7080401182174683},{"id":"https://openalex.org/C188045654","wikidata":"https://www.wikidata.org/wiki/Q17148339","display_name":"Memory bandwidth","level":2,"score":0.544714093208313},{"id":"https://openalex.org/C51290061","wikidata":"https://www.wikidata.org/wiki/Q1936765","display_name":"Uniform memory access","level":4,"score":0.5242079496383667},{"id":"https://openalex.org/C47487241","wikidata":"https://www.wikidata.org/wiki/Q5227230","display_name":"Data access","level":2,"score":0.5178154110908508},{"id":"https://openalex.org/C82687282","wikidata":"https://www.wikidata.org/wiki/Q66221","display_name":"Auxiliary memory","level":2,"score":0.5146340131759644},{"id":"https://openalex.org/C74193536","wikidata":"https://www.wikidata.org/wiki/Q574844","display_name":"Kernel (algebra)","level":2,"score":0.5079243779182434},{"id":"https://openalex.org/C176649486","wikidata":"https://www.wikidata.org/wiki/Q2308807","display_name":"Memory management","level":3,"score":0.501929759979248},{"id":"https://openalex.org/C63511323","wikidata":"https://www.wikidata.org/wiki/Q908936","display_name":"Interleaved memory","level":4,"score":0.47585341334342957},{"id":"https://openalex.org/C165696696","wikidata":"https://www.wikidata.org/wiki/Q11287","display_name":"Exploit","level":2,"score":0.45104432106018066},{"id":"https://openalex.org/C45374587","wikidata":"https://www.wikidata.org/wiki/Q12525525","display_name":"Computation","level":2,"score":0.41925686597824097},{"id":"https://openalex.org/C2778915421","wikidata":"https://www.wikidata.org/wiki/Q3643177","display_name":"Performance improvement","level":2,"score":0.41925132274627686},{"id":"https://openalex.org/C91481028","wikidata":"https://www.wikidata.org/wiki/Q1054686","display_name":"Distributed memory","level":3,"score":0.41776710748672485},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.39035171270370483},{"id":"https://openalex.org/C133875982","wikidata":"https://www.wikidata.org/wiki/Q764810","display_name":"Shared memory","level":2,"score":0.39014336466789246},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.21616727113723755},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.17198070883750916},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.09838467836380005},{"id":"https://openalex.org/C114614502","wikidata":"https://www.wikidata.org/wiki/Q76592","display_name":"Combinatorics","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0},{"id":"https://openalex.org/C21547014","wikidata":"https://www.wikidata.org/wiki/Q1423657","display_name":"Operations management","level":1,"score":0.0},{"id":"https://openalex.org/C38652104","wikidata":"https://www.wikidata.org/wiki/Q3510521","display_name":"Computer security","level":1,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/3394885.3431414","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3394885.3431414","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 26th Asia and South Pacific Design Automation Conference","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7","score":0.8500000238418579}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":10,"referenced_works":["https://openalex.org/W1863928786","https://openalex.org/W1988382391","https://openalex.org/W2058625399","https://openalex.org/W2093958639","https://openalex.org/W2143230897","https://openalex.org/W2293376937","https://openalex.org/W2584219348","https://openalex.org/W2792647449","https://openalex.org/W2980612421","https://openalex.org/W4253479694"],"related_works":["https://openalex.org/W2173219398","https://openalex.org/W4312916449","https://openalex.org/W87257424","https://openalex.org/W4232365528","https://openalex.org/W1975698617","https://openalex.org/W2409197925","https://openalex.org/W4295235956","https://openalex.org/W2989038266","https://openalex.org/W4297694018","https://openalex.org/W2794057488"],"abstract_inverted_index":{"Coarse-Grained":[0],"Reconfigurable":[1],"Architectures":[2],"(CGRAs)":[3],"are":[4,25,45],"attractive":[5],"reconfigurable":[6],"platforms":[7],"with":[8,31,120],"the":[9,23,29,38,64,80,97,104,110,132,139,142,151,172],"advantages":[10],"of":[11,106,141],"high":[12],"performance":[13,185],"and":[14,58,129,164],"power":[15],"efficiency.":[16],"In":[17,100],"a":[18,54,116,157,182],"CGRA":[19,30],"based":[20],"computing":[21],"system,":[22],"computations":[24],"often":[26,87],"mapped":[27],"onto":[28],"parallel":[32],"memory":[33,40,42,61,69,117,189],"accesses.":[34],"To":[35],"fully":[36],"exploit":[37],"on-chip":[39,91],"bandwidth,":[41],"partitioning":[43,70,118],"algorithms":[44,71],"widely":[46],"used":[47],"to":[48,63,95,102,150],"reduce":[49],"access":[50],"conflicts.":[51],"CGRAs":[52],"have":[53],"fixed":[55],"storage":[56,92],"fabric":[57],"limited":[59],"size":[60,140],"due":[62],"severe":[65],"area":[66],"constraints.":[67],"Previous":[68],"assumed":[72],"that":[73,137],"data":[74,127,161],"could":[75],"be":[76],"completely":[77],"transferred":[78],"into":[79,134],"target":[81,143],"memory.":[82,144],"However,":[83],"in":[84,109,160,168],"practice,":[85],"we":[86,113],"encounter":[88],"situations":[89],"where":[90],"is":[93,176],"insufficient":[94],"store":[96],"complete":[98],"data.":[99],"order":[101],"perform":[103],"computation":[105],"these":[107],"applications":[108],"memory-limited":[111],"CGRA,":[112],"first":[114],"develop":[115],"strategy":[119],"continual":[121],"placement,":[122],"which":[123],"can":[124,180],"also":[125],"avoid":[126],"preprocessing,":[128],"then":[130],"divide":[131],"kernel":[133],"multiple":[135],"subtasks":[136],"suit":[138],"Experimental":[145],"results":[146],"show":[147],"that,":[148],"compared":[149],"state-of-the-art":[152],"method,":[153],"our":[154,178],"approach":[155,179],"achieves":[156],"43.2%":[158],"reduction":[159],"preparation":[162],"time":[163],"an":[165],"18.5%":[166],"improvement":[167,186],"overall":[169,184],"performance.":[170],"If":[171],"subtask":[173],"generation":[174],"scheme":[175],"adopted,":[177],"achieve":[181],"14.4%":[183],"while":[187],"reducing":[188],"requirements":[190],"by":[191],"99.7%.":[192]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2022,"cited_by_count":1}],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}