{"id":"https://openalex.org/W3034950662","doi":"https://doi.org/10.1145/3386337","title":"Verilog HDL and its ancestors and descendants","display_name":"Verilog HDL and its ancestors and descendants","publication_year":2020,"publication_date":"2020-06-12","ids":{"openalex":"https://openalex.org/W3034950662","doi":"https://doi.org/10.1145/3386337","mag":"3034950662"},"language":"en","primary_location":{"id":"doi:10.1145/3386337","is_oa":true,"landing_page_url":"https://doi.org/10.1145/3386337","pdf_url":"https://dl.acm.org/doi/pdf/10.1145/3386337","source":{"id":"https://openalex.org/S4210216081","display_name":"Proceedings of the ACM on Programming Languages","issn_l":"2475-1421","issn":["2475-1421"],"is_oa":true,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319798","host_organization_name":"Association for Computing Machinery","host_organization_lineage":["https://openalex.org/P4310319798"],"host_organization_lineage_names":["Association for Computing Machinery"],"type":"journal"},"license":"public-domain","license_id":"https://openalex.org/licenses/public-domain","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the ACM on Programming Languages","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"diamond","oa_url":"https://dl.acm.org/doi/pdf/10.1145/3386337","any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5089238424","display_name":"Peter Flake","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Peter Flake","raw_affiliation_strings":["Elda Technology, UK"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Elda Technology, UK","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5085691551","display_name":"Phil Moorby","orcid":null},"institutions":[{"id":"https://openalex.org/I4210088467","display_name":"Pen Bay Medical Center","ror":"https://ror.org/007aefc66","country_code":"US","type":"healthcare","lineage":["https://openalex.org/I4210088467"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Phil Moorby","raw_affiliation_strings":["Rockport, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Rockport, USA","institution_ids":["https://openalex.org/I4210088467"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5090608944","display_name":"Steve Golson","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Steve Golson","raw_affiliation_strings":["Trilobyte Systems, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Trilobyte Systems, USA","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5059214654","display_name":"Arturo Salz","orcid":null},"institutions":[{"id":"https://openalex.org/I4210088951","display_name":"Synopsys (United States)","ror":"https://ror.org/013by2m91","country_code":"US","type":"company","lineage":["https://openalex.org/I4210088951"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Arturo Salz","raw_affiliation_strings":["Synopsys, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Synopsys, USA","institution_ids":["https://openalex.org/I4210088951"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5053477423","display_name":"Simon Davidmann","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Simon Davidmann","raw_affiliation_strings":["Imperas Software, UK"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Imperas Software, UK","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.9441,"has_fulltext":true,"cited_by_count":10,"citation_normalized_percentile":{"value":0.72474996,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":98},"biblio":{"volume":"4","issue":"HOPL","first_page":"1","last_page":"90"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9984999895095825,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9984999895095825,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10142","display_name":"Formal Methods in Verification","score":0.9983000159263611,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9980999827384949,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/verilog","display_name":"Verilog","score":0.9092843532562256},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7491433024406433},{"id":"https://openalex.org/keywords/register-transfer-level","display_name":"Register-transfer level","score":0.6746376752853394},{"id":"https://openalex.org/keywords/schematic","display_name":"Schematic","score":0.5901860594749451},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.5015356540679932},{"id":"https://openalex.org/keywords/electronic-circuit-design","display_name":"Electronic circuit design","score":0.4937468469142914},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.38073623180389404},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.31849053502082825},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.27528685331344604},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.2321707010269165},{"id":"https://openalex.org/keywords/circuit-design","display_name":"Circuit design","score":0.20285433530807495},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.12586531043052673},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.1251770555973053},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.07568278908729553},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.07301473617553711},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.07246005535125732}],"concepts":[{"id":"https://openalex.org/C2779030575","wikidata":"https://www.wikidata.org/wiki/Q827773","display_name":"Verilog","level":3,"score":0.9092843532562256},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7491433024406433},{"id":"https://openalex.org/C34854456","wikidata":"https://www.wikidata.org/wiki/Q1484552","display_name":"Register-transfer level","level":4,"score":0.6746376752853394},{"id":"https://openalex.org/C192328126","wikidata":"https://www.wikidata.org/wiki/Q4514647","display_name":"Schematic","level":2,"score":0.5901860594749451},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.5015356540679932},{"id":"https://openalex.org/C99149447","wikidata":"https://www.wikidata.org/wiki/Q5358339","display_name":"Electronic circuit design","level":3,"score":0.4937468469142914},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.38073623180389404},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.31849053502082825},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.27528685331344604},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.2321707010269165},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.20285433530807495},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.12586531043052673},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.1251770555973053},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.07568278908729553},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.07301473617553711},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.07246005535125732}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/3386337","is_oa":true,"landing_page_url":"https://doi.org/10.1145/3386337","pdf_url":"https://dl.acm.org/doi/pdf/10.1145/3386337","source":{"id":"https://openalex.org/S4210216081","display_name":"Proceedings of the ACM on Programming Languages","issn_l":"2475-1421","issn":["2475-1421"],"is_oa":true,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319798","host_organization_name":"Association for Computing Machinery","host_organization_lineage":["https://openalex.org/P4310319798"],"host_organization_lineage_names":["Association for Computing Machinery"],"type":"journal"},"license":"public-domain","license_id":"https://openalex.org/licenses/public-domain","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the ACM on Programming Languages","raw_type":"journal-article"}],"best_oa_location":{"id":"doi:10.1145/3386337","is_oa":true,"landing_page_url":"https://doi.org/10.1145/3386337","pdf_url":"https://dl.acm.org/doi/pdf/10.1145/3386337","source":{"id":"https://openalex.org/S4210216081","display_name":"Proceedings of the ACM on Programming Languages","issn_l":"2475-1421","issn":["2475-1421"],"is_oa":true,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319798","host_organization_name":"Association for Computing Machinery","host_organization_lineage":["https://openalex.org/P4310319798"],"host_organization_lineage_names":["Association for Computing Machinery"],"type":"journal"},"license":"public-domain","license_id":"https://openalex.org/licenses/public-domain","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the ACM on Programming Languages","raw_type":"journal-article"},"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","score":0.4099999964237213,"display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[],"has_content":{"pdf":true,"grobid_xml":true},"content_urls":{"pdf":"https://content.openalex.org/works/W3034950662.pdf","grobid_xml":"https://content.openalex.org/works/W3034950662.grobid-xml"},"referenced_works_count":48,"referenced_works":["https://openalex.org/W136232721","https://openalex.org/W616429135","https://openalex.org/W635909831","https://openalex.org/W770523223","https://openalex.org/W1490819086","https://openalex.org/W1492291048","https://openalex.org/W1505598781","https://openalex.org/W1526491617","https://openalex.org/W1533109738","https://openalex.org/W1537307653","https://openalex.org/W1714370737","https://openalex.org/W1967364882","https://openalex.org/W1971807768","https://openalex.org/W1991477326","https://openalex.org/W1994931168","https://openalex.org/W1996069313","https://openalex.org/W1996897268","https://openalex.org/W2001433161","https://openalex.org/W2004266858","https://openalex.org/W2007675081","https://openalex.org/W2045947732","https://openalex.org/W2064105914","https://openalex.org/W2064610754","https://openalex.org/W2071599593","https://openalex.org/W2093631848","https://openalex.org/W2105761964","https://openalex.org/W2120688461","https://openalex.org/W2743589154","https://openalex.org/W2758712168","https://openalex.org/W2911293636","https://openalex.org/W2912114176","https://openalex.org/W4206311840","https://openalex.org/W4212896057","https://openalex.org/W4214633034","https://openalex.org/W4234121747","https://openalex.org/W4234573855","https://openalex.org/W4234609313","https://openalex.org/W4235615007","https://openalex.org/W4237730125","https://openalex.org/W4240778276","https://openalex.org/W4245185858","https://openalex.org/W4247199268","https://openalex.org/W4247806563","https://openalex.org/W4251030308","https://openalex.org/W4253500907","https://openalex.org/W4253905895","https://openalex.org/W4254691308","https://openalex.org/W4392361663"],"related_works":["https://openalex.org/W2388933402","https://openalex.org/W1761969858","https://openalex.org/W2385740256","https://openalex.org/W2389932690","https://openalex.org/W4387024066","https://openalex.org/W2132512458","https://openalex.org/W3034950662","https://openalex.org/W1497276254","https://openalex.org/W2386257256","https://openalex.org/W4210564164"],"abstract_inverted_index":{"This":[0],"paper":[1],"describes":[2],"the":[3,6,32,38],"history":[4],"of":[5,34,43,66,70],"Verilog":[7,28,36,77],"hardware":[8],"description":[9],"language":[10],"(HDL),":[11],"including":[12],"its":[13,19,79],"influential":[14],"predecessors":[15],"and":[16,23,40,78],"successors.":[17],"Since":[18],"creation":[20],"in":[21,26,63],"1984":[22],"first":[24],"sale":[25],"1985,":[27],"has":[29],"completely":[30],"revolutionized":[31],"design":[33,73],"hardware.":[35],"enabled":[37],"development":[39],"wide":[41],"acceptance":[42],"logic":[44,49],"synthesis.":[45],"For":[46],"large-scale":[47],"digital":[48],"design,":[50],"previous":[51],"schematic-based":[52],"techniques":[53],"have":[54],"transformed":[55],"into":[56],"textual":[57],"register-transfer":[58],"level":[59],"(RTL)":[60],"descriptions":[61],"written":[62],"Verilog.":[64],"As":[65],"2018":[67],"about":[68],"80%":[69],"integrated":[71],"circuit":[72],"teams":[74],"worldwide":[75],"use":[76],"compatible":[80],"descendant":[81],"SystemVerilog.":[82]},"counts_by_year":[{"year":2025,"cited_by_count":4},{"year":2024,"cited_by_count":2},{"year":2023,"cited_by_count":1},{"year":2022,"cited_by_count":1},{"year":2021,"cited_by_count":2}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}