{"id":"https://openalex.org/W3083307249","doi":"https://doi.org/10.1145/3386263.3407587","title":"An In-memory Highly Reconfigurable Logic Circuit Based on Diode-assisted Enhanced Magnetoresistance Device","display_name":"An In-memory Highly Reconfigurable Logic Circuit Based on Diode-assisted Enhanced Magnetoresistance Device","publication_year":2020,"publication_date":"2020-09-04","ids":{"openalex":"https://openalex.org/W3083307249","doi":"https://doi.org/10.1145/3386263.3407587","mag":"3083307249"},"language":"en","primary_location":{"id":"doi:10.1145/3386263.3407587","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3386263.3407587","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2020 on Great Lakes Symposium on VLSI","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5012146181","display_name":"Zhe Huang","orcid":"https://orcid.org/0009-0002-4420-6601"},"institutions":[{"id":"https://openalex.org/I82880672","display_name":"Beihang University","ror":"https://ror.org/00wk2mp56","country_code":"CN","type":"education","lineage":["https://openalex.org/I82880672"]}],"countries":["CN"],"is_corresponding":true,"raw_author_name":"Zhe Huang","raw_affiliation_strings":["Beihang University, Beijing, China"],"affiliations":[{"raw_affiliation_string":"Beihang University, Beijing, China","institution_ids":["https://openalex.org/I82880672"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100333647","display_name":"Yue Zhang","orcid":"https://orcid.org/0000-0001-6893-7199"},"institutions":[{"id":"https://openalex.org/I82880672","display_name":"Beihang University","ror":"https://ror.org/00wk2mp56","country_code":"CN","type":"education","lineage":["https://openalex.org/I82880672"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Yue Zhang","raw_affiliation_strings":["Beihang University, Beijing, China"],"affiliations":[{"raw_affiliation_string":"Beihang University, Beijing, China","institution_ids":["https://openalex.org/I82880672"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100342286","display_name":"Kun Zhang","orcid":"https://orcid.org/0000-0001-7215-7953"},"institutions":[{"id":"https://openalex.org/I82880672","display_name":"Beihang University","ror":"https://ror.org/00wk2mp56","country_code":"CN","type":"education","lineage":["https://openalex.org/I82880672"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Kun Zhang","raw_affiliation_strings":["Beihang University, Beijing, China"],"affiliations":[{"raw_affiliation_string":"Beihang University, Beijing, China","institution_ids":["https://openalex.org/I82880672"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100685389","display_name":"Zhizhong Zhang","orcid":"https://orcid.org/0000-0002-5221-134X"},"institutions":[{"id":"https://openalex.org/I82880672","display_name":"Beihang University","ror":"https://ror.org/00wk2mp56","country_code":"CN","type":"education","lineage":["https://openalex.org/I82880672"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Zhizhong Zhang","raw_affiliation_strings":["Beihang University, Beijing, China"],"affiliations":[{"raw_affiliation_string":"Beihang University, Beijing, China","institution_ids":["https://openalex.org/I82880672"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5026852887","display_name":"Zhengdong Wang","orcid":"https://orcid.org/0000-0002-0435-1057"},"institutions":[{"id":"https://openalex.org/I82880672","display_name":"Beihang University","ror":"https://ror.org/00wk2mp56","country_code":"CN","type":"education","lineage":["https://openalex.org/I82880672"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Jinkai Wang","raw_affiliation_strings":["Beihang University, Beijing, China"],"affiliations":[{"raw_affiliation_string":"Beihang University, Beijing, China","institution_ids":["https://openalex.org/I82880672"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5018693228","display_name":"Youguang Zhang","orcid":"https://orcid.org/0009-0008-0928-4210"},"institutions":[{"id":"https://openalex.org/I82880672","display_name":"Beihang University","ror":"https://ror.org/00wk2mp56","country_code":"CN","type":"education","lineage":["https://openalex.org/I82880672"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Youguang Zhang","raw_affiliation_strings":["Beihang University, Beijing, China"],"affiliations":[{"raw_affiliation_string":"Beihang University, Beijing, China","institution_ids":["https://openalex.org/I82880672"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5066473925","display_name":"Weisheng Zhao","orcid":"https://orcid.org/0000-0001-8088-0404"},"institutions":[{"id":"https://openalex.org/I82880672","display_name":"Beihang University","ror":"https://ror.org/00wk2mp56","country_code":"CN","type":"education","lineage":["https://openalex.org/I82880672"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Weisheng Zhao","raw_affiliation_strings":["Beihang University, Hefei, China"],"affiliations":[{"raw_affiliation_string":"Beihang University, Hefei, China","institution_ids":["https://openalex.org/I82880672"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":7,"corresponding_author_ids":["https://openalex.org/A5012146181"],"corresponding_institution_ids":["https://openalex.org/I82880672"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.08114789,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"3","issue":null,"first_page":"259","last_page":"264"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12808","display_name":"Ferroelectric and Negative Capacitance Devices","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/magnetoresistive-random-access-memory","display_name":"Magnetoresistive random-access memory","score":0.7180044651031494},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6970398426055908},{"id":"https://openalex.org/keywords/programmable-logic-device","display_name":"Programmable logic device","score":0.528265118598938},{"id":"https://openalex.org/keywords/bottleneck","display_name":"Bottleneck","score":0.4915986955165863},{"id":"https://openalex.org/keywords/logic-family","display_name":"Logic family","score":0.4569019675254822},{"id":"https://openalex.org/keywords/logic-block","display_name":"Logic block","score":0.4565112888813019},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.4531843364238739},{"id":"https://openalex.org/keywords/non-volatile-memory","display_name":"Non-volatile memory","score":0.4373829662799835},{"id":"https://openalex.org/keywords/adder","display_name":"Adder","score":0.4290008842945099},{"id":"https://openalex.org/keywords/von-neumann-architecture","display_name":"Von Neumann architecture","score":0.4102875590324402},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.38680869340896606},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.3697385787963867},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.36640089750289917},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.36072060465812683},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.2696932256221771},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.1941564381122589},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.17968204617500305},{"id":"https://openalex.org/keywords/random-access-memory","display_name":"Random access memory","score":0.08156237006187439},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.07809144258499146}],"concepts":[{"id":"https://openalex.org/C46891859","wikidata":"https://www.wikidata.org/wiki/Q1061546","display_name":"Magnetoresistive random-access memory","level":3,"score":0.7180044651031494},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6970398426055908},{"id":"https://openalex.org/C206274596","wikidata":"https://www.wikidata.org/wiki/Q1063837","display_name":"Programmable logic device","level":2,"score":0.528265118598938},{"id":"https://openalex.org/C2780513914","wikidata":"https://www.wikidata.org/wiki/Q18210350","display_name":"Bottleneck","level":2,"score":0.4915986955165863},{"id":"https://openalex.org/C162454741","wikidata":"https://www.wikidata.org/wiki/Q173359","display_name":"Logic family","level":4,"score":0.4569019675254822},{"id":"https://openalex.org/C2778325283","wikidata":"https://www.wikidata.org/wiki/Q1125244","display_name":"Logic block","level":3,"score":0.4565112888813019},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.4531843364238739},{"id":"https://openalex.org/C177950962","wikidata":"https://www.wikidata.org/wiki/Q10997658","display_name":"Non-volatile memory","level":2,"score":0.4373829662799835},{"id":"https://openalex.org/C164620267","wikidata":"https://www.wikidata.org/wiki/Q376953","display_name":"Adder","level":3,"score":0.4290008842945099},{"id":"https://openalex.org/C80469333","wikidata":"https://www.wikidata.org/wiki/Q189088","display_name":"Von Neumann architecture","level":2,"score":0.4102875590324402},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.38680869340896606},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.3697385787963867},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.36640089750289917},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.36072060465812683},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.2696932256221771},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.1941564381122589},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.17968204617500305},{"id":"https://openalex.org/C2994168587","wikidata":"https://www.wikidata.org/wiki/Q5295","display_name":"Random access memory","level":2,"score":0.08156237006187439},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.07809144258499146},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/3386263.3407587","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3386263.3407587","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2020 on Great Lakes Symposium on VLSI","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.7699999809265137,"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":19,"referenced_works":["https://openalex.org/W98793950","https://openalex.org/W1981943579","https://openalex.org/W1983096721","https://openalex.org/W1985330137","https://openalex.org/W2058466440","https://openalex.org/W2061361388","https://openalex.org/W2072610908","https://openalex.org/W2214682759","https://openalex.org/W2331009326","https://openalex.org/W2583234992","https://openalex.org/W2593172471","https://openalex.org/W2756167909","https://openalex.org/W2769168016","https://openalex.org/W2884227506","https://openalex.org/W2889746799","https://openalex.org/W2911423181","https://openalex.org/W2941172511","https://openalex.org/W3125984961","https://openalex.org/W4292169167"],"related_works":["https://openalex.org/W2342993049","https://openalex.org/W2167086449","https://openalex.org/W2139569078","https://openalex.org/W4252227487","https://openalex.org/W2135291096","https://openalex.org/W2477544739","https://openalex.org/W4248303983","https://openalex.org/W2141429499","https://openalex.org/W2102341772","https://openalex.org/W2039867690"],"abstract_inverted_index":{"In":[0,106],"the":[1,8,43,73,100,139,153,171],"post-Moore":[2],"era,":[3],"in":[4,85,174],"order":[5],"to":[6,72],"solve":[7],"problem":[9],"of":[10,20,45,75,99,103,142,148],"von":[11],"Neumann":[12],"bottleneck":[13],"and":[14,22,48,67,78,95,151,177],"memory":[15,21,33,86],"wall":[16],"caused":[17],"by":[18],"separation":[19],"processor,":[23],"in-memory-processing":[24],"(IMP)":[25],"technique":[26],"has":[27],"aroused":[28],"great":[29],"attention.":[30],"Novel":[31],"non-volatile":[32],"(NVM)":[34],"based":[35,57,117],"on":[36,58,118],"spintronic":[37,55],"devices":[38],"shows":[39],"promise":[40],"for":[41,51,182],"satisfying":[42],"needs":[44],"low-power":[46],"consumption":[47,91],"high":[49,101],"speed":[50],"IMP.":[52],"However,":[53],"most":[54],"memories":[56],"magnetic":[59],"tunnel":[60],"junctions":[61],"(MTJs)":[62],"can":[63,126,156,168],"only":[64],"implement":[65,158],"simple":[66],"specific":[68],"logic":[69,83,115,130],"functions":[70,84,131,160],"due":[71],"limits":[74],"single":[76],"device":[77],"circuit":[79,116,125,135,155,167],"structure.":[80],"Otherwise,":[81],"performing":[82],"generates":[87],"vast":[88],"dynamic":[89],"power":[90],"during":[92],"frequent":[93],"reading":[94],"writing":[96],"processes":[97],"because":[98],"resistance":[102],"miniaturized":[104],"MTJ.":[105],"this":[107],"paper,":[108],"we":[109],"propose":[110],"an":[111],"in-memory":[112,184],"highly":[113],"reconfigurable":[114,166],"diode-assisted":[119],"enhanced":[120],"magnetoresistance":[121],"(DEMR)":[122],"device.":[123,144],"Our":[124],"realize":[127],"16":[128],"different":[129,175],"with":[132],"extremely":[133],"limited":[134],"area":[136],"benefiting":[137],"from":[138],"special":[140],"structure":[141],"DEMR":[143],"With":[145],"appropriate":[146],"adjustment":[147],"control":[149],"bit":[150],"current,":[152],"proposed":[154,165],"further":[157],"complex":[159],"like":[161],"full":[162],"adder.":[163],"The":[164],"flexibly":[169],"meet":[170],"performance":[172],"requirements":[173],"scenarios":[176],"will":[178],"contribute":[179],"a":[180],"lot":[181],"future":[183],"chip":[185],"design.":[186]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}