{"id":"https://openalex.org/W3083686196","doi":"https://doi.org/10.1145/3386263.3406920","title":"A Simplified Arm Processor for VLSI Education","display_name":"A Simplified Arm Processor for VLSI Education","publication_year":2020,"publication_date":"2020-09-04","ids":{"openalex":"https://openalex.org/W3083686196","doi":"https://doi.org/10.1145/3386263.3406920","mag":"3083686196"},"language":"en","primary_location":{"id":"doi:10.1145/3386263.3406920","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3386263.3406920","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2020 on Great Lakes Symposium on VLSI","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5050259862","display_name":"Noah Boorstin","orcid":null},"institutions":[{"id":"https://openalex.org/I133543626","display_name":"Harvey Mudd College","ror":"https://ror.org/025ecfn45","country_code":"US","type":"education","lineage":["https://openalex.org/I133543626"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Noah Boorstin","raw_affiliation_strings":["Harvey Mudd College, Claremont, CA, USA"],"affiliations":[{"raw_affiliation_string":"Harvey Mudd College, Claremont, CA, USA","institution_ids":["https://openalex.org/I133543626"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5073233151","display_name":"Veronica Cortes","orcid":null},"institutions":[{"id":"https://openalex.org/I133543626","display_name":"Harvey Mudd College","ror":"https://ror.org/025ecfn45","country_code":"US","type":"education","lineage":["https://openalex.org/I133543626"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Veronica Cortes","raw_affiliation_strings":["Harvey Mudd College, Claremont, CA, USA"],"affiliations":[{"raw_affiliation_string":"Harvey Mudd College, Claremont, CA, USA","institution_ids":["https://openalex.org/I133543626"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5045969210","display_name":"Kaveh Pezeshki","orcid":"https://orcid.org/0000-0003-4363-185X"},"institutions":[{"id":"https://openalex.org/I133543626","display_name":"Harvey Mudd College","ror":"https://ror.org/025ecfn45","country_code":"US","type":"education","lineage":["https://openalex.org/I133543626"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Kaveh Pezeshki","raw_affiliation_strings":["Harvey Mudd College, Claremont, CA, USA"],"affiliations":[{"raw_affiliation_string":"Harvey Mudd College, Claremont, CA, USA","institution_ids":["https://openalex.org/I133543626"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101661944","display_name":"David Harris","orcid":"https://orcid.org/0000-0001-9075-5965"},"institutions":[{"id":"https://openalex.org/I133543626","display_name":"Harvey Mudd College","ror":"https://ror.org/025ecfn45","country_code":"US","type":"education","lineage":["https://openalex.org/I133543626"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"David Harris","raw_affiliation_strings":["Harvey Mudd College, Claremont, CA, USA"],"affiliations":[{"raw_affiliation_string":"Harvey Mudd College, Claremont, CA, USA","institution_ids":["https://openalex.org/I133543626"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5016747709","display_name":"Shuojin Hang","orcid":null},"institutions":[{"id":"https://openalex.org/I2801109035","display_name":"ARM (United Kingdom)","ror":"https://ror.org/04mmhzs81","country_code":"GB","type":"company","lineage":["https://openalex.org/I2801109035"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Shuojin Hang","raw_affiliation_strings":["Arm Ltd., Cambridge, United Kingdom"],"affiliations":[{"raw_affiliation_string":"Arm Ltd., Cambridge, United Kingdom","institution_ids":["https://openalex.org/I2801109035"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5050259862"],"corresponding_institution_ids":["https://openalex.org/I133543626"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.24301784,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"555","last_page":"559"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11283","display_name":"Experimental Learning in Engineering","score":0.9987999796867371,"subfield":{"id":"https://openalex.org/subfields/2214","display_name":"Media Technology"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11283","display_name":"Experimental Learning in Engineering","score":0.9987999796867371,"subfield":{"id":"https://openalex.org/subfields/2214","display_name":"Media Technology"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9965000152587891,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9957000017166138,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/datapath","display_name":"Datapath","score":0.9043375253677368},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.7475002408027649},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7265762090682983},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.6983065605163574},{"id":"https://openalex.org/keywords/schematic","display_name":"Schematic","score":0.6277076601982117},{"id":"https://openalex.org/keywords/standard-cell","display_name":"Standard cell","score":0.6086349487304688},{"id":"https://openalex.org/keywords/debugging","display_name":"Debugging","score":0.5907987952232361},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5458557605743408},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.51518714427948},{"id":"https://openalex.org/keywords/application-specific-integrated-circuit","display_name":"Application-specific integrated circuit","score":0.5113305449485779},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.45351898670196533},{"id":"https://openalex.org/keywords/block","display_name":"Block (permutation group theory)","score":0.4398317039012909},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.4372761845588684},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.41086962819099426},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.25450068712234497},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.23177701234817505},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.1782953441143036},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.13726353645324707},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.11930370330810547}],"concepts":[{"id":"https://openalex.org/C2781198647","wikidata":"https://www.wikidata.org/wiki/Q1633673","display_name":"Datapath","level":2,"score":0.9043375253677368},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.7475002408027649},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7265762090682983},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.6983065605163574},{"id":"https://openalex.org/C192328126","wikidata":"https://www.wikidata.org/wiki/Q4514647","display_name":"Schematic","level":2,"score":0.6277076601982117},{"id":"https://openalex.org/C78401558","wikidata":"https://www.wikidata.org/wiki/Q464496","display_name":"Standard cell","level":3,"score":0.6086349487304688},{"id":"https://openalex.org/C168065819","wikidata":"https://www.wikidata.org/wiki/Q845566","display_name":"Debugging","level":2,"score":0.5907987952232361},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5458557605743408},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.51518714427948},{"id":"https://openalex.org/C77390884","wikidata":"https://www.wikidata.org/wiki/Q217302","display_name":"Application-specific integrated circuit","level":2,"score":0.5113305449485779},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.45351898670196533},{"id":"https://openalex.org/C2777210771","wikidata":"https://www.wikidata.org/wiki/Q4927124","display_name":"Block (permutation group theory)","level":2,"score":0.4398317039012909},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.4372761845588684},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.41086962819099426},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.25450068712234497},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.23177701234817505},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.1782953441143036},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.13726353645324707},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.11930370330810547},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/3386263.3406920","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3386263.3406920","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2020 on Great Lakes Symposium on VLSI","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":2,"referenced_works":["https://openalex.org/W1520275403","https://openalex.org/W2101331965"],"related_works":["https://openalex.org/W2889102485","https://openalex.org/W2388299947","https://openalex.org/W2113599973","https://openalex.org/W4385831984","https://openalex.org/W3047211184","https://openalex.org/W2070693700","https://openalex.org/W2158494242","https://openalex.org/W2169589717","https://openalex.org/W4243638536","https://openalex.org/W2134697552"],"abstract_inverted_index":{"This":[0],"paper":[1],"describes":[2],"a":[3,17,27,42,92,106],"simplified":[4],"Arm":[5],"processor":[6,11,62],"for":[7,74,112],"VLSI":[8],"education.":[9],"The":[10,61,79,89,100,127],"implements":[12],"an":[13,35,163],"8-bit":[14],"datapath":[15],"and":[16,59,63,86,94,115,117,119,148,161],"subset":[18],"of":[19,44,70,105,109,121,124,153],"the":[20,75,98,113,122,125,134,137,151,154],"instructions":[21],"so":[22],"that":[23],"it":[24,96],"fits":[25],"on":[26],"1.5":[28,30],"x":[29],"mm":[31],"MOSIS":[32],"TinyChip":[33],"in":[34],"ON":[36],"Semiconductor":[37],"0.6":[38],"um":[39],"process.":[40],"During":[41],"sequence":[43],"four":[45],"labs,":[46,155],"students":[47,156],"learn":[48],"digital":[49],"integrated":[50],"circuit":[51],"design":[52,104],"with":[53],"commercial":[54],"CAD":[55],"tools":[56],"from":[57],"Cadence":[58],"Synopsys.":[60],"cell":[64,84],"library":[65],"are":[66,157],"provided,":[67],"missing":[68],"one":[69],"each":[71],"interesting":[72],"component":[73],"student":[76],"to":[77,97,136,159],"design.":[78],"first":[80],"lab":[81,129,141],"covers":[82],"leaf":[83],"schematic":[85],"layout":[87],"entry.":[88],"second":[90],"generates":[91],"wordslice":[93],"adds":[95],"datapath.":[99],"third":[101],"involves":[102,143],"hand":[103],"small":[107],"block":[108],"random":[110],"logic":[111,144],"aludecoder,":[114],"synthesis":[116],"placement":[118],"routing":[120],"rest":[123],"controller.":[126],"fourth":[128],"completes":[130],"chip":[131],"assembly,":[132],"connecting":[133],"components":[135],"pad":[138],"frame.":[139],"Each":[140],"also":[142],"verification,":[145],"DRC,":[146],"LVS,":[147],"debug.":[149],"At":[150],"end":[152],"prepared":[158],"define":[160],"complete":[162],"open-ended":[164],"final":[165],"project":[166],"chip.":[167]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
