{"id":"https://openalex.org/W3107461983","doi":"https://doi.org/10.1145/3380446.3430690","title":"Accelerating Chip Design with Machine Learning","display_name":"Accelerating Chip Design with Machine Learning","publication_year":2020,"publication_date":"2020-11-16","ids":{"openalex":"https://openalex.org/W3107461983","doi":"https://doi.org/10.1145/3380446.3430690","mag":"3107461983"},"language":"en","primary_location":{"id":"doi:10.1145/3380446.3430690","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3380446.3430690","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2020 ACM/IEEE Workshop on Machine Learning for CAD","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5010156116","display_name":"Brucek Khailany","orcid":"https://orcid.org/0000-0002-7584-3489"},"institutions":[{"id":"https://openalex.org/I4210127875","display_name":"Nvidia (United States)","ror":"https://ror.org/03jdj4y14","country_code":"US","type":"company","lineage":["https://openalex.org/I4210127875"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Brucek Khailany","raw_affiliation_strings":["NVIDIA, Austin, TX, USA"],"affiliations":[{"raw_affiliation_string":"NVIDIA, Austin, TX, USA","institution_ids":["https://openalex.org/I4210127875"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":["https://openalex.org/A5010156116"],"corresponding_institution_ids":["https://openalex.org/I4210127875"],"apc_list":null,"apc_paid":null,"fwci":1.0374,"has_fulltext":false,"cited_by_count":20,"citation_normalized_percentile":{"value":0.77070069,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":93,"max":99},"biblio":{"volume":null,"issue":null,"first_page":"33","last_page":"33"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9984999895095825,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/moores-law","display_name":"Moore's law","score":0.7689465880393982},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7077794075012207},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.5792674422264099},{"id":"https://openalex.org/keywords/integrated-circuit-design","display_name":"Integrated circuit design","score":0.5356433391571045},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.5180395245552063},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.49727562069892883},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4359338879585266},{"id":"https://openalex.org/keywords/efficient-energy-use","display_name":"Efficient energy use","score":0.4346204102039337},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4135507047176361},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.3779858946800232},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.18102982640266418},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.13886785507202148},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.09197583794593811},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.09158727526664734}],"concepts":[{"id":"https://openalex.org/C206891323","wikidata":"https://www.wikidata.org/wiki/Q178655","display_name":"Moore's law","level":2,"score":0.7689465880393982},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7077794075012207},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.5792674422264099},{"id":"https://openalex.org/C74524168","wikidata":"https://www.wikidata.org/wiki/Q1074539","display_name":"Integrated circuit design","level":2,"score":0.5356433391571045},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.5180395245552063},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.49727562069892883},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4359338879585266},{"id":"https://openalex.org/C2742236","wikidata":"https://www.wikidata.org/wiki/Q924713","display_name":"Efficient energy use","level":2,"score":0.4346204102039337},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4135507047176361},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.3779858946800232},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.18102982640266418},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.13886785507202148},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.09197583794593811},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.09158727526664734},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/3380446.3430690","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3380446.3430690","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2020 ACM/IEEE Workshop on Machine Learning for CAD","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7","score":0.8899999856948853}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":3,"referenced_works":["https://openalex.org/W2163605009","https://openalex.org/W2519887557","https://openalex.org/W3088618441"],"related_works":["https://openalex.org/W176583869","https://openalex.org/W2038859986","https://openalex.org/W2104315811","https://openalex.org/W2142217172","https://openalex.org/W1929041301","https://openalex.org/W4230312832","https://openalex.org/W2110366946","https://openalex.org/W1982273910","https://openalex.org/W2170610805","https://openalex.org/W2137747828"],"abstract_inverted_index":{"As":[0,47],"Moore's":[1],"law":[2],"has":[3],"provided":[4],"an":[5],"exponential":[6],"increase":[7],"in":[8,19,57],"chip":[9],"transistor":[10],"density,":[11],"the":[12,37,58],"unique":[13],"features":[14],"we":[15,61],"can":[16],"now":[17],"include":[18],"large":[20],"chips":[21],"are":[22,33],"no":[23],"longer":[24],"predominantly":[25],"limited":[26,35],"by":[27,36],"area":[28],"constraints.":[29],"Instead,":[30],"new":[31],"capabilities":[32],"increasingly":[34],"engineering":[38],"effort":[39,67],"associated":[40],"with":[41],"digital":[42],"design,":[43],"verification,":[44],"and":[45,52,65],"implementation.":[46],"applications":[48],"demand":[49],"more":[50],"performance":[51],"energy":[53],"efficiency":[54],"from":[55],"specialization":[56],"post-Moore's-law":[59],"era,":[60],"expect":[62],"required":[63],"complexity":[64],"design":[66],"to":[68],"increase.":[69]},"counts_by_year":[{"year":2026,"cited_by_count":2},{"year":2025,"cited_by_count":3},{"year":2024,"cited_by_count":5},{"year":2023,"cited_by_count":4},{"year":2022,"cited_by_count":4},{"year":2021,"cited_by_count":2}],"updated_date":"2026-03-27T14:29:43.386196","created_date":"2025-10-10T00:00:00"}