{"id":"https://openalex.org/W3032097305","doi":"https://doi.org/10.1145/3378678.3391877","title":"Compiling synchronous languages to optimal move code for exposed datapath architectures","display_name":"Compiling synchronous languages to optimal move code for exposed datapath architectures","publication_year":2020,"publication_date":"2020-05-25","ids":{"openalex":"https://openalex.org/W3032097305","doi":"https://doi.org/10.1145/3378678.3391877","mag":"3032097305"},"language":"en","primary_location":{"id":"doi:10.1145/3378678.3391877","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3378678.3391877","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 23th International Workshop on Software and Compilers for Embedded Systems","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5076382835","display_name":"Marc Dahlem","orcid":"https://orcid.org/0000-0003-3877-8179"},"institutions":[{"id":"https://openalex.org/I4210109972","display_name":"Insiders Technologies (Germany)","ror":"https://ror.org/0179g4w23","country_code":"DE","type":"company","lineage":["https://openalex.org/I4210109972"]}],"countries":["DE"],"is_corresponding":true,"raw_author_name":"Marc Dahlem","raw_affiliation_strings":["Insiders Technologies GmbH, Kaiserslautern, Germany"],"affiliations":[{"raw_affiliation_string":"Insiders Technologies GmbH, Kaiserslautern, Germany","institution_ids":["https://openalex.org/I4210109972"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5081184867","display_name":"Klaus Schneider","orcid":"https://orcid.org/0000-0002-1305-7132"},"institutions":[{"id":"https://openalex.org/I153267046","display_name":"University of Kaiserslautern","ror":"https://ror.org/04zrf7b53","country_code":"DE","type":"education","lineage":["https://openalex.org/I153267046"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Klaus Schneider","raw_affiliation_strings":["University of Kaiserslautern, Kaiserslautern, Germany"],"affiliations":[{"raw_affiliation_string":"University of Kaiserslautern, Kaiserslautern, Germany","institution_ids":["https://openalex.org/I153267046"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5076382835"],"corresponding_institution_ids":["https://openalex.org/I4210109972"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.06518583,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"28","issue":null,"first_page":"19","last_page":"25"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10933","display_name":"Real-Time Systems Scheduling","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/datapath","display_name":"Datapath","score":0.9434261918067932},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8450022339820862},{"id":"https://openalex.org/keywords/compiler","display_name":"Compiler","score":0.7285348176956177},{"id":"https://openalex.org/keywords/dataflow","display_name":"Dataflow","score":0.7024620771408081},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.6658698320388794},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.6647783517837524},{"id":"https://openalex.org/keywords/asynchronous-communication","display_name":"Asynchronous communication","score":0.6011916399002075},{"id":"https://openalex.org/keywords/instruction-level-parallelism","display_name":"Instruction-level parallelism","score":0.5959438681602478},{"id":"https://openalex.org/keywords/code-generation","display_name":"Code generation","score":0.5376871824264526},{"id":"https://openalex.org/keywords/asynchrony","display_name":"Asynchrony (computer programming)","score":0.4874110519886017},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.4818354845046997},{"id":"https://openalex.org/keywords/parallelism","display_name":"Parallelism (grammar)","score":0.4814719259738922},{"id":"https://openalex.org/keywords/control-flow","display_name":"Control flow","score":0.43682217597961426},{"id":"https://openalex.org/keywords/register-allocation","display_name":"Register allocation","score":0.43483367562294006},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.37141066789627075},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.3466795086860657},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.1467406153678894}],"concepts":[{"id":"https://openalex.org/C2781198647","wikidata":"https://www.wikidata.org/wiki/Q1633673","display_name":"Datapath","level":2,"score":0.9434261918067932},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8450022339820862},{"id":"https://openalex.org/C169590947","wikidata":"https://www.wikidata.org/wiki/Q47506","display_name":"Compiler","level":2,"score":0.7285348176956177},{"id":"https://openalex.org/C96324660","wikidata":"https://www.wikidata.org/wiki/Q205446","display_name":"Dataflow","level":2,"score":0.7024620771408081},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.6658698320388794},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.6647783517837524},{"id":"https://openalex.org/C151319957","wikidata":"https://www.wikidata.org/wiki/Q752739","display_name":"Asynchronous communication","level":2,"score":0.6011916399002075},{"id":"https://openalex.org/C140763907","wikidata":"https://www.wikidata.org/wiki/Q2714055","display_name":"Instruction-level parallelism","level":3,"score":0.5959438681602478},{"id":"https://openalex.org/C133162039","wikidata":"https://www.wikidata.org/wiki/Q1061077","display_name":"Code generation","level":3,"score":0.5376871824264526},{"id":"https://openalex.org/C2779019669","wikidata":"https://www.wikidata.org/wiki/Q25203946","display_name":"Asynchrony (computer programming)","level":3,"score":0.4874110519886017},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.4818354845046997},{"id":"https://openalex.org/C2781172179","wikidata":"https://www.wikidata.org/wiki/Q853109","display_name":"Parallelism (grammar)","level":2,"score":0.4814719259738922},{"id":"https://openalex.org/C160191386","wikidata":"https://www.wikidata.org/wiki/Q868299","display_name":"Control flow","level":2,"score":0.43682217597961426},{"id":"https://openalex.org/C128916667","wikidata":"https://www.wikidata.org/wiki/Q1343660","display_name":"Register allocation","level":3,"score":0.43483367562294006},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.37141066789627075},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.3466795086860657},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.1467406153678894},{"id":"https://openalex.org/C26517878","wikidata":"https://www.wikidata.org/wiki/Q228039","display_name":"Key (lock)","level":2,"score":0.0},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/3378678.3391877","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3378678.3391877","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 23th International Workshop on Software and Compilers for Embedded Systems","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":44,"referenced_works":["https://openalex.org/W12949374","https://openalex.org/W1578088218","https://openalex.org/W1579041286","https://openalex.org/W1663179985","https://openalex.org/W1672891595","https://openalex.org/W1674952968","https://openalex.org/W1875492031","https://openalex.org/W1952695700","https://openalex.org/W1968513265","https://openalex.org/W2003531456","https://openalex.org/W2004414305","https://openalex.org/W2052649320","https://openalex.org/W2055928880","https://openalex.org/W2060008798","https://openalex.org/W2066453638","https://openalex.org/W2099808324","https://openalex.org/W2100500718","https://openalex.org/W2124114495","https://openalex.org/W2125023624","https://openalex.org/W2125415493","https://openalex.org/W2127335869","https://openalex.org/W2142501475","https://openalex.org/W2147345262","https://openalex.org/W2149803907","https://openalex.org/W2156993372","https://openalex.org/W2171732229","https://openalex.org/W2172212694","https://openalex.org/W2173702800","https://openalex.org/W2186806377","https://openalex.org/W2229305353","https://openalex.org/W2319731145","https://openalex.org/W2399145680","https://openalex.org/W2399343913","https://openalex.org/W2565417786","https://openalex.org/W2622045392","https://openalex.org/W2768980428","https://openalex.org/W2798901509","https://openalex.org/W2798994962","https://openalex.org/W2892326913","https://openalex.org/W2898343707","https://openalex.org/W2952721922","https://openalex.org/W3150407013","https://openalex.org/W4206245103","https://openalex.org/W4246797854"],"related_works":["https://openalex.org/W1486267685","https://openalex.org/W2131391942","https://openalex.org/W1941899280","https://openalex.org/W1983193863","https://openalex.org/W2137204728","https://openalex.org/W1917361244","https://openalex.org/W2133877928","https://openalex.org/W4301736542","https://openalex.org/W2987630328","https://openalex.org/W1551927567"],"abstract_inverted_index":{"Conventional":[0],"processor":[1,27],"architectures":[2,28],"are":[3],"limited":[4],"in":[5],"exploiting":[6],"instruction":[7],"level":[8],"parallelism":[9],"(ILP).":[10],"One":[11],"of":[12,23,39,75],"the":[13,34,53,73],"reasons":[14],"for":[15],"this":[16],"limitation":[17],"is":[18,60,69],"their":[19,30],"relatively":[20],"low":[21],"number":[22],"registers.":[24,76],"Thus,":[25],"recent":[26],"expose":[29],"datapaths":[31],"so":[32],"that":[33],"compiler":[35],"can":[36],"take":[37],"care":[38],"directly":[40],"transporting":[41],"results":[42],"from":[43],"processing":[44,48],"units":[45],"to":[46,70],"other":[47],"units.":[49],"Among":[50],"these":[51],"architectures,":[52],"Synchronous":[54],"Control":[55],"Asynchronous":[56],"Dataflow":[57],"(SCAD)":[58],"architecture":[59,66],"a":[61],"recently":[62],"proposed":[63],"exposed":[64],"datapath":[65],"whose":[67],"goal":[68],"completely":[71],"bypass":[72],"use":[74]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
