{"id":"https://openalex.org/W3012103594","doi":"https://doi.org/10.1145/3373376.3378517","title":"A Computational Temporal Logic for Superconducting Accelerators","display_name":"A Computational Temporal Logic for Superconducting Accelerators","publication_year":2020,"publication_date":"2020-03-09","ids":{"openalex":"https://openalex.org/W3012103594","doi":"https://doi.org/10.1145/3373376.3378517","mag":"3012103594"},"language":"en","primary_location":{"id":"doi:10.1145/3373376.3378517","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3373376.3378517","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the Twenty-Fifth International Conference on Architectural Support for Programming Languages and Operating Systems","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5019627345","display_name":"Georgios Tzimpragos","orcid":"https://orcid.org/0000-0002-0127-4703"},"institutions":[{"id":"https://openalex.org/I154570441","display_name":"University of California, Santa Barbara","ror":"https://ror.org/02t274463","country_code":"US","type":"education","lineage":["https://openalex.org/I154570441"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Georgios Tzimpragos","raw_affiliation_strings":["University of California, Santa Barbara, Santa Barbara, CA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of California, Santa Barbara, Santa Barbara, CA, USA","institution_ids":["https://openalex.org/I154570441"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5076654998","display_name":"Dilip Vasudevan","orcid":"https://orcid.org/0000-0003-0931-309X"},"institutions":[{"id":"https://openalex.org/I148283060","display_name":"Lawrence Berkeley National Laboratory","ror":"https://ror.org/02jbv0t02","country_code":"US","type":"facility","lineage":["https://openalex.org/I1330989302","https://openalex.org/I148283060","https://openalex.org/I39565521"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Dilip Vasudevan","raw_affiliation_strings":["Lawrence Berkeley National Laboratory, Berkeley, CA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Lawrence Berkeley National Laboratory, Berkeley, CA, USA","institution_ids":["https://openalex.org/I148283060"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5076231412","display_name":"Nestan Tsiskaridze","orcid":"https://orcid.org/0000-0002-4729-9770"},"institutions":[{"id":"https://openalex.org/I154570441","display_name":"University of California, Santa Barbara","ror":"https://ror.org/02t274463","country_code":"US","type":"education","lineage":["https://openalex.org/I154570441"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Nestan Tsiskaridze","raw_affiliation_strings":["University of California, Santa Barbara, Santa Barbara, CA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of California, Santa Barbara, Santa Barbara, CA, USA","institution_ids":["https://openalex.org/I154570441"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5038069067","display_name":"George Michelogiannakis","orcid":"https://orcid.org/0000-0003-3743-6054"},"institutions":[{"id":"https://openalex.org/I148283060","display_name":"Lawrence Berkeley National Laboratory","ror":"https://ror.org/02jbv0t02","country_code":"US","type":"facility","lineage":["https://openalex.org/I1330989302","https://openalex.org/I148283060","https://openalex.org/I39565521"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"George Michelogiannakis","raw_affiliation_strings":["Lawrence Berkeley National Laboratory, Berkeley, CA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Lawrence Berkeley National Laboratory, Berkeley, CA, USA","institution_ids":["https://openalex.org/I148283060"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5038802680","display_name":"Advait Madhavan","orcid":"https://orcid.org/0000-0002-4121-1336"},"institutions":[{"id":"https://openalex.org/I1321296531","display_name":"National Institute of Standards and Technology","ror":"https://ror.org/05xpvk416","country_code":"US","type":"funder","lineage":["https://openalex.org/I1321296531","https://openalex.org/I1343035065"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Advait Madhavan","raw_affiliation_strings":["National Institute of Standards and Technology &amp; University of Maryland, Gaithersburg, MD, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"National Institute of Standards and Technology &amp; University of Maryland, Gaithersburg, MD, USA","institution_ids":["https://openalex.org/I1321296531"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5103035410","display_name":"Jennifer Volk","orcid":"https://orcid.org/0009-0007-2540-3964"},"institutions":[{"id":"https://openalex.org/I154570441","display_name":"University of California, Santa Barbara","ror":"https://ror.org/02t274463","country_code":"US","type":"education","lineage":["https://openalex.org/I154570441"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Jennifer Volk","raw_affiliation_strings":["University of California, Santa Barbara, Santa Barbara, CA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of California, Santa Barbara, Santa Barbara, CA, USA","institution_ids":["https://openalex.org/I154570441"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5010873686","display_name":"John Shalf","orcid":"https://orcid.org/0000-0002-0608-3690"},"institutions":[{"id":"https://openalex.org/I148283060","display_name":"Lawrence Berkeley National Laboratory","ror":"https://ror.org/02jbv0t02","country_code":"US","type":"facility","lineage":["https://openalex.org/I1330989302","https://openalex.org/I148283060","https://openalex.org/I39565521"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"John Shalf","raw_affiliation_strings":["Lawrence Berkeley National Laboratory, Berkeley, CA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Lawrence Berkeley National Laboratory, Berkeley, CA, USA","institution_ids":["https://openalex.org/I148283060"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5036932071","display_name":"Timothy Sherwood","orcid":"https://orcid.org/0000-0002-6550-6075"},"institutions":[{"id":"https://openalex.org/I154570441","display_name":"University of California, Santa Barbara","ror":"https://ror.org/02t274463","country_code":"US","type":"education","lineage":["https://openalex.org/I154570441"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Timothy Sherwood","raw_affiliation_strings":["University of California, Santa Barbara, Santa Barbara, CA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of California, Santa Barbara, Santa Barbara, CA, USA","institution_ids":["https://openalex.org/I154570441"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":8,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":3.5382,"has_fulltext":false,"cited_by_count":47,"citation_normalized_percentile":{"value":0.93365541,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":94,"max":99},"biblio":{"volume":null,"issue":null,"first_page":"435","last_page":"448"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9984999895095825,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.690132200717926},{"id":"https://openalex.org/keywords/predicate-logic","display_name":"Predicate logic","score":0.6829255223274231},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.6000672578811646},{"id":"https://openalex.org/keywords/computation","display_name":"Computation","score":0.580702006816864},{"id":"https://openalex.org/keywords/logic-family","display_name":"Logic family","score":0.4998128414154053},{"id":"https://openalex.org/keywords/pass-transistor-logic","display_name":"Pass transistor logic","score":0.4863725006580353},{"id":"https://openalex.org/keywords/resistor\u2013transistor-logic","display_name":"Resistor\u2013transistor logic","score":0.46498391032218933},{"id":"https://openalex.org/keywords/theoretical-computer-science","display_name":"Theoretical computer science","score":0.45356130599975586},{"id":"https://openalex.org/keywords/logic-optimization","display_name":"Logic optimization","score":0.4370945692062378},{"id":"https://openalex.org/keywords/logic-simulation","display_name":"Logic simulation","score":0.41582706570625305},{"id":"https://openalex.org/keywords/temporal-logic","display_name":"Temporal logic","score":0.41348618268966675},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.4129728078842163},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.3944207727909088},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.38940978050231934},{"id":"https://openalex.org/keywords/digital-electronics","display_name":"Digital electronics","score":0.32612597942352295},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.2916772961616516},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.24482539296150208},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.23437944054603577},{"id":"https://openalex.org/keywords/description-logic","display_name":"Description logic","score":0.21275103092193604},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.0966758131980896}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.690132200717926},{"id":"https://openalex.org/C19689857","wikidata":"https://www.wikidata.org/wiki/Q4055684","display_name":"Predicate logic","level":3,"score":0.6829255223274231},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.6000672578811646},{"id":"https://openalex.org/C45374587","wikidata":"https://www.wikidata.org/wiki/Q12525525","display_name":"Computation","level":2,"score":0.580702006816864},{"id":"https://openalex.org/C162454741","wikidata":"https://www.wikidata.org/wiki/Q173359","display_name":"Logic family","level":4,"score":0.4998128414154053},{"id":"https://openalex.org/C198521697","wikidata":"https://www.wikidata.org/wiki/Q7142438","display_name":"Pass transistor logic","level":4,"score":0.4863725006580353},{"id":"https://openalex.org/C180405849","wikidata":"https://www.wikidata.org/wiki/Q173464","display_name":"Resistor\u2013transistor logic","level":5,"score":0.46498391032218933},{"id":"https://openalex.org/C80444323","wikidata":"https://www.wikidata.org/wiki/Q2878974","display_name":"Theoretical computer science","level":1,"score":0.45356130599975586},{"id":"https://openalex.org/C28449271","wikidata":"https://www.wikidata.org/wiki/Q6667469","display_name":"Logic optimization","level":4,"score":0.4370945692062378},{"id":"https://openalex.org/C64859876","wikidata":"https://www.wikidata.org/wiki/Q173673","display_name":"Logic simulation","level":3,"score":0.41582706570625305},{"id":"https://openalex.org/C25016198","wikidata":"https://www.wikidata.org/wiki/Q781833","display_name":"Temporal logic","level":2,"score":0.41348618268966675},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.4129728078842163},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.3944207727909088},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.38940978050231934},{"id":"https://openalex.org/C81843906","wikidata":"https://www.wikidata.org/wiki/Q173156","display_name":"Digital electronics","level":3,"score":0.32612597942352295},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.2916772961616516},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.24482539296150208},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.23437944054603577},{"id":"https://openalex.org/C102993220","wikidata":"https://www.wikidata.org/wiki/Q387196","display_name":"Description logic","level":2,"score":0.21275103092193604},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.0966758131980896}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/3373376.3378517","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3373376.3378517","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the Twenty-Fifth International Conference on Architectural Support for Programming Languages and Operating Systems","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.8700000047683716,"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7"}],"awards":[{"id":"https://openalex.org/G4118504369","display_name":null,"funder_award_id":"1740352; 1730309; 1717779; 1563935","funder_id":"https://openalex.org/F4320306076","funder_display_name":"National Science Foundation"}],"funders":[{"id":"https://openalex.org/F4320306076","display_name":"National Science Foundation","ror":"https://ror.org/021nxhr62"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":33,"referenced_works":["https://openalex.org/W1576295179","https://openalex.org/W1583806922","https://openalex.org/W1995363554","https://openalex.org/W2034913792","https://openalex.org/W2042279090","https://openalex.org/W2070992435","https://openalex.org/W2086800445","https://openalex.org/W2087873353","https://openalex.org/W2088068734","https://openalex.org/W2098171268","https://openalex.org/W2119587409","https://openalex.org/W2128830021","https://openalex.org/W2151934333","https://openalex.org/W2162211413","https://openalex.org/W2218744901","https://openalex.org/W2260769207","https://openalex.org/W2266823799","https://openalex.org/W2281833458","https://openalex.org/W2322516248","https://openalex.org/W2339427061","https://openalex.org/W2353270203","https://openalex.org/W2725880994","https://openalex.org/W2741755328","https://openalex.org/W2791606710","https://openalex.org/W2802559652","https://openalex.org/W2883012749","https://openalex.org/W2913341486","https://openalex.org/W2933264412","https://openalex.org/W2952257392","https://openalex.org/W2955978272","https://openalex.org/W2999951176","https://openalex.org/W3105474961","https://openalex.org/W4233569121"],"related_works":["https://openalex.org/W2789662562","https://openalex.org/W2077986289","https://openalex.org/W4231839681","https://openalex.org/W1999759102","https://openalex.org/W4251160711","https://openalex.org/W2132855573","https://openalex.org/W589757979","https://openalex.org/W2079982495","https://openalex.org/W1852211506","https://openalex.org/W4244281133"],"abstract_inverted_index":{"Superconducting":[0],"logic":[1,22,34,118,148],"offers":[2],"the":[3,20,32,40,61,78,130,151,156,190],"potential":[4],"to":[5,73,76,144],"perform":[6],"computation":[7],"at":[8],"tremendous":[9],"speeds":[10],"and":[11,31,97,154,162,165,186],"energy":[12],"savings.":[13],"However,":[14],"a":[15,29,48,54,84,95,141,145,173,180],"\"semantic":[16],"gap\"":[17],"lies":[18],"between":[19,126,133],"level-driven":[21],"that":[23,35,67,116,129,155],"traditional":[24],"hardware":[25],"designs":[26],"accept":[27],"as":[28],"foundation":[30],"pulse-driven":[33],"is":[36,83],"naturally":[37,120],"supported":[38],"by":[39],"most":[41],"compelling":[42],"superconducting":[43,64,102,117,194],"technologies.":[44],"A":[45],"pulse,":[46],"unlike":[47],"level":[49],"signal,":[50],"will":[51],"fire":[52],"through":[53,140,172],"channel":[55],"for":[56,101],"only":[57],"an":[58,187],"instant.":[59],"Arranging":[60],"network":[62],"of":[63,80,105,175,183,192],"components":[65],"so":[66],"input":[68],"pulses":[69],"always":[70],"arrive":[71],"simultaneously":[72],"\"logic":[74],"gates''":[75],"maintain":[77],"illusion":[79],"Boolean-only":[81],"evaluation":[82,188],"significant":[85],"engineering":[86],"hurdle.":[87],"In":[88],"this":[89],"paper,":[90],"we":[91,114],"explore":[92],"computing":[93],"in":[94,111,150,189],"new":[96],"more":[98],"native":[99],"tongue":[100],"logic:":[103],"time":[104],"arrival.":[106],"Building":[107],"on":[108],"recent":[109],"work":[110],"delay-based":[112],"computations":[113],"show":[115],"can":[119,137,159],"compute":[121],"directly":[122],"over":[123],"temporal":[124,146],"relationships":[125,132],"pulse":[127,135],"arrivals,":[128],"computational":[131],"those":[134],"arrivals":[136],"be":[138],"formalized":[139],"functional":[142],"extension":[143],"predicate":[147],"used":[149],"verification":[152],"community,":[153],"resulting":[157],"architectures":[158],"operate":[160],"asynchronously":[161],"describe":[163],"real":[164],"useful":[166],"computations.":[167],"We":[168],"verify":[169],"our":[170,184],"hypothesis":[171],"combination":[174],"detailed":[176],"analog":[177],"circuit":[178],"models,":[179],"formal":[181],"analysis":[182],"abstractions,":[185],"context":[191],"several":[193],"accelerators.":[195]},"counts_by_year":[{"year":2025,"cited_by_count":4},{"year":2024,"cited_by_count":9},{"year":2023,"cited_by_count":10},{"year":2022,"cited_by_count":12},{"year":2021,"cited_by_count":10},{"year":2020,"cited_by_count":2}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}
