{"id":"https://openalex.org/W3007361144","doi":"https://doi.org/10.1145/3373087.3375383","title":"A Top-Down Design Methodology for Synthesizing FPGA Fabrics Using Standard ASIC Flow","display_name":"A Top-Down Design Methodology for Synthesizing FPGA Fabrics Using Standard ASIC Flow","publication_year":2020,"publication_date":"2020-02-23","ids":{"openalex":"https://openalex.org/W3007361144","doi":"https://doi.org/10.1145/3373087.3375383","mag":"3007361144"},"language":"en","primary_location":{"id":"doi:10.1145/3373087.3375383","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3373087.3375383","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2020 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5102143677","display_name":"Prashanth Mohan","orcid":null},"institutions":[{"id":"https://openalex.org/I74973139","display_name":"Carnegie Mellon University","ror":"https://ror.org/05x2bcf33","country_code":"US","type":"education","lineage":["https://openalex.org/I74973139"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Prashanth Mohan","raw_affiliation_strings":["Carnegie Mellon University, Pittsburgh, PA, USA"],"affiliations":[{"raw_affiliation_string":"Carnegie Mellon University, Pittsburgh, PA, USA","institution_ids":["https://openalex.org/I74973139"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5078208066","display_name":"Oguz Atli","orcid":null},"institutions":[{"id":"https://openalex.org/I74973139","display_name":"Carnegie Mellon University","ror":"https://ror.org/05x2bcf33","country_code":"US","type":"education","lineage":["https://openalex.org/I74973139"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Oguz Atli","raw_affiliation_strings":["Carnegie Mellon University, Pittsburgh, PA, USA"],"affiliations":[{"raw_affiliation_string":"Carnegie Mellon University, Pittsburgh, PA, USA","institution_ids":["https://openalex.org/I74973139"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5068915909","display_name":"Onur Kibar","orcid":null},"institutions":[{"id":"https://openalex.org/I74973139","display_name":"Carnegie Mellon University","ror":"https://ror.org/05x2bcf33","country_code":"US","type":"education","lineage":["https://openalex.org/I74973139"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Onur O. Kibar","raw_affiliation_strings":["Carnegie Mellon University, Pittsburgh, PA, USA"],"affiliations":[{"raw_affiliation_string":"Carnegie Mellon University, Pittsburgh, PA, USA","institution_ids":["https://openalex.org/I74973139"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5000377660","display_name":"Ken Mai","orcid":"https://orcid.org/0000-0002-9096-8757"},"institutions":[{"id":"https://openalex.org/I74973139","display_name":"Carnegie Mellon University","ror":"https://ror.org/05x2bcf33","country_code":"US","type":"education","lineage":["https://openalex.org/I74973139"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Ken Mai","raw_affiliation_strings":["Carnegie Mellon University, Pittsburgh, PA, USA"],"affiliations":[{"raw_affiliation_string":"Carnegie Mellon University, Pittsburgh, PA, USA","institution_ids":["https://openalex.org/I74973139"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5102143677"],"corresponding_institution_ids":["https://openalex.org/I74973139"],"apc_list":null,"apc_paid":null,"fwci":0.5137,"has_fulltext":false,"cited_by_count":7,"citation_normalized_percentile":{"value":0.63386183,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"313","last_page":"313"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9988999962806702,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9980999827384949,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/application-specific-integrated-circuit","display_name":"Application-specific integrated circuit","score":0.8965590000152588},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.830561101436615},{"id":"https://openalex.org/keywords/design-flow","display_name":"Design flow","score":0.6858968734741211},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6407477855682373},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5133227705955505},{"id":"https://openalex.org/keywords/flow","display_name":"Flow (mathematics)","score":0.4978907108306885},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4853314459323883},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.06874063611030579}],"concepts":[{"id":"https://openalex.org/C77390884","wikidata":"https://www.wikidata.org/wiki/Q217302","display_name":"Application-specific integrated circuit","level":2,"score":0.8965590000152588},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.830561101436615},{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.6858968734741211},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6407477855682373},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5133227705955505},{"id":"https://openalex.org/C38349280","wikidata":"https://www.wikidata.org/wiki/Q1434290","display_name":"Flow (mathematics)","level":2,"score":0.4978907108306885},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4853314459323883},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.06874063611030579},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/3373087.3375383","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3373087.3375383","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2020 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W3010492628","https://openalex.org/W2144630005","https://openalex.org/W2356927082","https://openalex.org/W2134422574","https://openalex.org/W2114354660","https://openalex.org/W1589309932","https://openalex.org/W1604320855","https://openalex.org/W1716741439","https://openalex.org/W2126880757","https://openalex.org/W2152926077"],"abstract_inverted_index":{"Design":[0],"methodologies":[1],"for":[2,98,200],"synthesizing":[3],"FPGA":[4,30,58,111,122,143,160,179],"fabrics":[5,180,196],"presented":[6],"in":[7,20,135,162,211],"the":[8,28,46,57,96,110,115,126,136,141,147,159,189,198],"literature":[9],"typically":[10],"employ":[11],"a":[12,34,49,67,88,105,167,182],"bottom-up":[13,35],"approach":[14],"wherein":[15],"individual":[16],"tiles":[17,55],"are":[18],"synthesized":[19],"isolation":[21],"and":[22,72,100,145,150,157,177,194],"later":[23],"stitched":[24],"together":[25],"to":[26,37,45,154],"generate":[27],"large":[29],"fabric.":[31,59,112],"However,":[32],"using":[33,125],"methodology":[36,91,191],"ensure":[38],"fabric-level":[39],"performance":[40,212],"targets":[41],"is":[42,92],"challenging":[43],"due":[44],"lack":[47],"of":[48,69,109,175],"global":[50,106],"timing":[51,107,151,173],"view":[52,108],"across":[53,213],"multiple":[54,214],"spanning":[56],"While":[60],"previous":[61],"works":[62],"address":[63],"this":[64,86],"problem":[65],"with":[66,166],"combination":[68],"manual":[70,101,202],"buffering":[71,102,203],"floorplanning,":[73],"these":[74],"additional":[75],"steps":[76],"introduce":[77],"significant":[78],"deviations":[79],"from":[80],"standard":[81,168],"push-button":[82],"ASIC":[83],"flows.":[84],"In":[85],"paper,":[87],"top-down":[89,190],"synthesis":[90],"proposed,":[93],"which":[94],"eliminates":[95],"need":[97,199],"floorplanning":[99,205],"by":[103],"providing":[104,207],"To":[113],"evaluate":[114],"proposed":[116],"design":[117],"methodology,":[118],"we":[119],"developed":[120],"an":[121],"fabric":[123,132,161],"generator":[124,133],"Chisel":[127],"hardware":[128],"construction":[129],"language.":[130],"The":[131],"reads":[134],"Verilog-to-Routing":[137],"architecture":[138],"file,":[139],"describing":[140],"user-defined":[142],"fabric,":[144],"generates":[146],"Verilog":[148],"netlist":[149],"exceptions":[152],"required":[153],"automatically":[155],"place":[156,193],"route":[158,195],"any":[163,201],"technology":[164],"node":[165],"cell":[169],"library.":[170],"Post":[171],"layout":[172],"analysis":[174],"placed":[176],"routed":[178],"on":[181],"28nm":[183],"industrial":[184],"CMOS":[185],"process":[186],"demonstrates":[187],"that":[188],"can":[192],"without":[197],"or":[204],"while":[206],"~20%":[208],"average":[209],"improvement":[210],"benchmark":[215],"designs.":[216]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2024,"cited_by_count":1},{"year":2022,"cited_by_count":1},{"year":2021,"cited_by_count":2},{"year":2020,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
